Addressing Mode Register (Amr); Addressing Mode Register (Amr) Field Descriptions - Texas Instruments TMS320C67X Reference Manual

Control Register File
2.7.3

Addressing Mode Register (AMR)

Figure 2−3. Addressing Mode Register (AMR)
31
Reserved
R-0
15 14 13
B7 MODE B6 MODE
R/W-0 R/W-0
Legend: R = Readable by the MVC instruction; W = Writeable by the MVC instruction; -n = value after reset
Table 2−5. Addressing Mode Register (AMR) Field Descriptions
Bit Field
31−26 Reserved
25−21 BK1
20−16 BK0
15−14 B7 MODE
2-10 CPU Data Paths and Control
For each of the eight registers (A4–A7, B4–B7) that can perform linear or circu-
lar addressing, the addressing mode register (AMR) specifies the addressing
mode. A 2-bit field for each register selects the address modification mode:
linear (the default) or circular mode. With circular addressing, the field also
specifies which BK (block size) field to use for a circular buffer. In addition, the
buffer must be aligned on a byte boundary equal to the block size. The mode
select fields and block size fields are shown in Figure 2−3 and described in
Table 2−5.
26 25
12 11 10 9
B5 MODE B4 MODE
R/W-0 R/W-0
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
0−1Fh Block size field 1. A 5-bit value used in calculating block sizes for circular
addressing. Table 2−6 shows block size calculations for all 32 possibilities.
Block size (in bytes) = 2
0−1Fh Block size field 0. A 5-bit value used in calculating block sizes for circular
addressing. Table 2−6 shows block size calculations for all 32 possibilities.
Block size (in bytes) = 2
0−3h Address mode selection for register file B7.
0 Linear modification (default at reset)
1h Circular addressing using the BK0 field
2h Circular addressing using the BK1 field
3h Reserved
21 20
BK1
R/W-0
8 7 6 5
A7 MODE A6 MODE
R/W-0 R/W-0
(N+1)
, where N is the 5-bit value in BK1
(N+1)
, where N is the 5-bit value in BK0
BK0
R/W-0
4 3 2 1
A5 MODE A4 MODE
R/W-0 R/W-0
SPRU733
16
0