Data Receive Register (Drr); Data Receive Register (Drr) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

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11.1

Data Receive Register (DRR)

The data receive register (DRR) contains the value to be written to the data bus
Table 11-5). For devices with an EDMA controller, DRR is mapped to memory locations on both the
EDMA bus (data port) and the peripheral bus (configuration bus). See the device-specific datasheet for
the memory address of these registers. DRR is accessible via the peripheral bus and via the EDMA bus.
Both the CPU and the EDMA controller can access DRR in all the memory-mapped locations. An access
to any EDMA bus location is equivalent to an access to DRR of the corresponding McBSP. For example,
a read from any word-aligned address in a DRR location on the EDMA bus is equivalent to a read from
the DRR of the corresponding McBSP on the peripheral bus. The EDMA controller should be set up to use
the EDMA bus for serial port servicing, freeing up the peripheral bus for other functions.
31
LEGEND: R = Read only; -n = value after reset
Bit Field
31-0 DR
SPRU580E – December 2005
Figure 11-1. Data Receive Register (DRR)
Table 11-5. Data Receive Register (DRR) Field Descriptions
Value Description
0-FFFF FFFFh Data receive register value to be written to the data bus.
0
DR
R-0

Data Receive Register (DRR)

(Figure 11-1 and
0
Registers 81