Status Register (Tms320C30 Andtms320C31); Status Register (Tms320C32 Only); Status (St) Register - Texas Instruments TMS320C3x User Manual

3.1.7

Status (ST) Register

Figure 3–3. Status Register (TMS320C30 andTMS320C31)
31 – 16 15 14
xx
xx xx
Notes: 1) xx = reserved bit, read as 0
2) R = read, W = write
Figure 3–4. Status Register (TMS320C32 Only)
31 – 16 15 14
PRGW INT
xx
status config
R R/W
Notes: 1) xx = reserved bit, read as 0
2) R = read, W = write
The status (ST) register contains global information about the state of the CPU.
Operations usually set the condition flags of the status register according to
whether the result is 0, negative, etc. This includes register load and store
operations as well as arithmetic and logical functions. However, when the
status register is loaded, the contents of the source operand replace the ST's
contents bit for bit, regardless of the state of any bits in the source operand.
Following an ST load, the contents of the status register are identical to the
contents of the source operand. This allows the status register to be saved
easily and restored. At system reset, a 0 is written to this register.
Figure 3–3 shows the format of the status register for the 'C30 and 'C31 devices.
Figure 3–4 shows the format of the status register for the 'C32 device. Table 3–2
describes the status register bits, their names, and their functions.
13 12 11 10
GIE CC CE CF
R/W R/W R/W R/W
13 12 11 10
GIE CC CE CF
R/W R/W R/W R/W
9 8 7 6
xx RM OVM LUF
R/W R/W R/W
9 8 7 6
xx RM OVM LUF
R/W R/W R/W
CPU Multiport Register File
5 4 3 2
LV UF N Z
R/W R/W R/W R/W
5 4 3 2
LV UF N Z
R/W R/W R/W R/W
CPU Registers
1 0
V C
R/W R/W
1 0
V C
R/W R/W
3-5