Pll Multiplier Control Register (Pllm); Pllc0 Pre-Divider Control Register (Prediv); Pll Multiplier Control Register (Pllm) Field Descriptions; Pllc0 Pre-Divider Control Register (Prediv) Field Descriptions - Texas Instruments AM1802 Reference Manual

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7.3.9 PLL Multiplier Control Register (PLLM)

The PLL multiplier control register (PLLM) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit Field Value
31-5 Reserved 0
4-0 PLLM 0-1Fh

7.3.10 PLLC0 Pre-Divider Control Register (PREDIV)

The PLLC0 pre-divider control register (PREDIV) is shown in
31
15 14
PREDEN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit Field Value
31-14 Reserved 0
15 PREDEN
0
1
14-5 Reserved 0
4-0 RATIO 0-1Fh
SPRUGX5A – May 2011
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Figure 7-10. PLL Multiplier Control Register (PLLM)
Reserved
Reserved
R-0
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
Figure 7-11. PLLC0 Pre-Divider Control Register (PREDIV)
Reserved
Reserved
R-0
Description
Reserved
PLLC0 pre-divider enable.
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
PLLC0 pre-divider is enabled.
Reserved
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
Copyright © 2011, Texas Instruments Incorporated
Figure 7-10 and described in
R-0
5 4
Figure 7-11
R-0
5
Phase-Locked Loop Controller (PLLC)
PLLC Registers
Table 7-12.
PLLM
R/W-13h
and described in Table 7-13.
4
RATIO
R/W-0
16
0
16
0
85