Control Status Register (Csr); Pwrd Field Of Control Status Register (Csr) - Texas Instruments TMS320C67X Reference Manual

2.7.4

Control Status Register (CSR)

Figure 2−4. Control Status Register (CSR)
31
CPU ID
15
PWRD
R/W-0
Legend: R = Readable by the MVC instruction; W = Writeable by the MVC instruction; WC = Bit is cleared on write; -n = value
after reset; -x = value is indeterminate after reset
†
See the device-specific data manual for the default value of this field.
Figure 2−5. PWRD Field of Control Status Register (CSR)
15
Reserved Enabled or nonenabled interrupt wake
R/W-0
Legend: R = Readable by the MVC instruction; W = Writeable by the MVC instruction; -n = value after reset
SPRU733
The control status register (CSR) contains control and status bits. The CSR
is shown in Figure 2−4 and described in Table 2−7. For the PWRD, EN, PCC,
and DCC fields, see the device-specific data manual to see if it supports the
options that these fields control.
The power-down modes and their wake-up methods are programmed by the
PWRD field (bits 15−10) of CSR. The PWRD field of CSR is shown in
Figure 2−5. When writing to CSR, all bits of the PWRD field should be
configured at the same time. A logic 0 should be used when writing to the
reserved bit (bit 15) of the PWRD field.
R-0
10 9
SAT EN
R/WC-0 R-x
14
R/W-0
24 23
8 7 5 4
PCC
R/W-0
13
Enabled interrupt wake
R/W-0
CPU Data Paths and Control
Control Register File
REVISION ID
R-x †
2 1
DCC PGIE
R/W-0 R/W-0
12 11
PD3 PD2
R/W-0 R/W-0
16
0
GIE
R/W-0
10
PD1
R/W-0
2-13