General Gpio Topology Guidelines; Example Gpio[7:0] Topology Level Shifted Guideline; Generic Gpio[7:0] Topology Guideline; Gpio[7:0]L General Routing Guideline - Intel Quark SoC X1000 Design Manual

13.4

General GPIO Topology Guidelines

This section describes the layout recommendations for GPIO signals [7:0].
Figure 45.

Example GPIO[7:0] Topology level shifted Guideline

SoC
CFIOHVTEW NO RCOMP
Figure 46.

Generic GPIO[7:0] Topology Guideline

CFIOHVTEW NO RCOMP
Table 50.

GPIO[7:0]l General Routing Guideline

PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Single-
ended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Trace Spacing(S3): Between GPIO
and other signals
Trace Segment Length
Stub length
®
Intel Quark™ SoC X1000
PDG
94
®
Intel
Breakout
L L
A B
SoC
Breakout
L
A
Quark™ SoC X1000—Asynchronous Signals Design Guidelines
SCHOTTKY_4P
ESD Diode
Rs
L L
C
D1
Rs
L
B
Breakout
4 Layer 4 Layer
L L
A B
MS MS
50 Ω +/- 15%
4.2 mil 4.2 mil
4.2 mil 10 mil
4.2 mil 10 mil
min = 0.2"
0.5"
max = 0.8"
Less than 1400 mils
Rs
Connector
L L
D2 D3
Connector
L
C
4 Layer 4 Layer
L L L L
C D1/ D2/ D3
MS MS
4.2 mil 4.2 mil
10 mil 10 mil
10 mil 10 mil
min = 0.1"
0.25" max
max = 2.5"
June 2014
Order Number: 330258-002US