Spi Flash Design Guidelines; Serial Peripheral Interface (Spi) General Introduction; Description; Serial Peripheral Interface (Spi) Signal Description - Intel Quark SoC X1000 Design Manual

SPI Flash Design Guidelines—Intel
11.0

SPI Flash Design Guidelines

11.1

Serial Peripheral Interface (SPI) General Introduction

The following provides general guidelines for compatibility and design
recommendations for supporting flash devices.
11.1.1

Description

®
Intel Quark™ SoC X1000 supports three integrated Serial Peripheral Interface (SPI)
4-pin interfaces that provides a potentially lower-cost alternative for system flash.The
Legacy SPI interface is specifically for the system boot flash and the additional two
interfaces are for general purpose use. Each Serial Peripheral Interface is used to
support a SPI compatible flash device via an independent GPIO chip select pin. Each
SPI flash device can be up to 64 MBytes (512 Mbits). SoC drives the SPI Interface at
either 20 MHz (legacy SPI) or 25Mhz.
11.2

Serial Peripheral Interface (SPI) Signal Description

Table 43.

SPI Signals

Signal Name
LSPI_MOSI
LSPI_MISO
LSPI_CLK
LSPI_SS_B
SPI0_MOSI
SPI1_MOSI
SPI0_MISO
SPI1_MISO
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
SPI0_SCK
SPI1_SCK
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Group
Legacy SPI serial output data from Intel
Data
the SPI flash device.
Legacy SPI serial input data from the SPI flash device to Intel
Data
Quark™ SoC X1000.
Clock Legacy SPI Clock output from Intel
Chip Select Legacy SPI chip select
SPI serial output data from Intel
Data
flash device.
SPI serial input data from the SPI flash device to Intel
Data
SoC X1000
Chip Select SPI chip selects for SPI 0 Interface
Chip Select SPI chip select for SPI 1 Interface
Clock SPI Clock output from
Description
®
Quark™ SoC X1000 to
®
Quark™ SoC X1000
®
Quark™ SoC X1000 to the SPI
®
Quark™
®
Intel Quark™ SoC X1000
®
PDG
81