Table of Contents
Advertisement
CHAPTER 10
PHYSICAL DESIGN AND SYSTEM DEBUGGING
An Intel486™ processor system can easily be implemented using standard interface logic,
DRAMs, EPROMs or Flash, and I/O devices. The clock speeds of Intel486 processor family sys-
tems require some design guidelines. This chapter outlines the basic design issues, ranging from
power and ground issues to achieving the proper thermal environment for the Intel486 processor.
10.1 GENERAL SYSTEM GUIDELINES
The proper operation of any system depends on proper physical layout. The layout issues and de-
sign guidelines presented in this chapter are relevant to both higher- and lower-frequency system
design implementation.
The improvement of integrated circuit technology has led to an enormous increase in the number
of functions that are being implemented on a single chip. Improved technology allows higher
clock frequencies. The Intel486 processor, with bus operating frequencies of 25 MHz/33 MHz
and corresponding high edge rates and internal clock multiplication, presents a challenge to the
conventional interconnection technologies which to date have been adequate for interconnecting
less sophisticated devices. This challenge especially applies to system designers who are respon-
sible for providing suitable interconnections at the system level.
The interconnections in a circuit behave like transmission lines which degrade the system's over-
all speed and distort output waveforms.
In laying out a conventional printed circuit board, there is freedom in defining the length, shape
and sequence of interconnections. But with devices such as the Intel486 processor, this task
should be carried out with careful planning, evaluation, and testing of the wiring patterns. It is
also critical to understand the physical properties of transmission lines because interconnection
at high edge rates is analogous to a transmission line.
10.2 POWER DISSIPATION AND DISTRIBUTION
The Intel486 processor uses one-micron or smaller CHMOS IV process technology. The main
difference between the previous HMOS microprocessors and the more recent versions is that
power dissipation is primarily capacitive, and there is almost no D.C. power dissipation. Because
power dissipation is directly proportional to frequency, accommodating high-speed signals on
printed circuit boards and through the interconnections is critical. The power dissipation of the
Very Large Scale Integration (VLSI) device in operation is expressed by the sum of the power
dissipation of the circuit elements, which include internal logic gates, I/O buffers and cache
RAMs. It is also a function of the operating conditions.
10-1
Advertisement
Chapters
Table of Contents
