Topology Guidelines; Spi0 Topology - Intel Quark SoC X1000 Design Manual

9.3

Topology Guidelines

This section contains preliminary information and details for layout and routing
guidelines for the general-purpose SPI interfaces.
Figure 33.

SPI0 Topology

Table 35. SPI0_MOSI, SPI0_SCK
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Single-
ended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Trace Spacing(S3): Between GPIO
and other signals
Trace Segment Length
Note: * Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
Table 36. SPI0_MISO
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Single-
ended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
®
Intel Quark™ SoC X1000
PDG
68
®
Intel Quark™ SoC X1000—General Purpose SPI Interface Design Guidelines
SoC
Breakout
L
A
Rs
L L
B C
Breakout
4 Layer 4 Layer
L L
A B
MS MS
50 Ω +/- 10%
4.2 mil 4.2 mil
4.2 mil 10 mil
4.2 mil 10 mil
0.5" max 0.1" - 0.8"
Breakout
4 Layer 4 Layer
L L
A B
MS MS
50 Ω +/- 10%
4.2 mil 4.2 mil
4.2 mil 10 mil
SPI Slave
L
D
4 Layer 4 Layer
L L
C D
MS MS
4.2 mil 4.2 mil
10 mil 4.2 mil
10 mil 4.2 mil
0.1" - 3.0" 0.5" max
4 Layer 4 Layer
L L
C D
MS MS
4.2 mil 4.2 mil
10 mil 4.2 mil
June 2014
Order Number: 330258-002US