Intel Quark SoC X1000 Design Manual page 179

General Differential Signals Design Guidelines—Intel
• Differential signals should not cross any plane splits or voids. However, it may be
necessary for a trace to be partially routed over a via anti-pad void in the chipset
escape area. The amount of the trace that is over the void should be minimized in
the length and percentage of the width of the trace. At worst, no more than half of
the trace width should be over the via anti-pad at any given time.
— If crossing a plane split is necessary, proper placement of stitching caps can
minimize the adverse effects on EMI and signal quality performance caused by
crossing the split. Stitching capacitors are small-valued capacitors (1 µF or
lower in value) that bridge voltage plane splits close to where high-speed
signals or clocks cross the plane split. The capacitor ends should tie to each
plane separated by the split. They are also used to bridge, or bypass, power
and ground planes close to where a high-speed signal changes layers.
— As an example of bridging plane splits, a plane split that separates V
V
crossing. One side of the cap should tie to V
V
plane splits. They minimize the impedance discontinuity and current loop area
that crossing a plane split creates.
June 2014
Order Number: 330258-002US
®
planes should have a stitching cap placed near any high-speed signal
CC3_3
. Stitching caps provide a high frequency current return path across
CC3_3
Quark™ SoC X1000
and the other side should tie to
5REF
§ §
and
5REF
®
Intel Quark™ SoC X1000
PDG
179