Design Checklist Items; Esd Checklist - Intel Quark SoC X1000 Design Manual

18.4

Design Checklist Items

This section provides a checklist that should be reviewed during the design process.
This checklist has been developed over time and experience to reduce the possibility of
unwanted ESD risk. The checklist is shown below. Not every suggestion is 100%
effective; attention to appropriate items can help reduce ESD risk. The design and
layout of the board must be reviewed by the appropriate ESD engineer assigned to the
project prior to committing to fabrication.
Table 61.

ESD Checklist

ITEM
NO.
173-1
173-2
173-3
®
Intel Quark™ SoC X1000
PDG
138
All hot-plug interfaces, should have ESD protection present.
Implement a ground shape continuous along the board edge, outside of any traces. Keep
the gap between the ground shape and other shapes or traces at least 20 mils. The
minimum shape neck width is 50 mils. The minimum fill area should be 20% of the
connector footprint under each connector.
Add stitching vias throughout the length of the ground shape, no more than 300 mils
apart, close to the board's edge (connector holes can be considered stitching vias).
®
Intel Quark™ SoC X1000—Electrostatic Discharge (ESD)
DESCRIPTION
§ §
Y/N
June 2014
Order Number: 330258-002US