Spi1 Topology - Intel Quark SoC X1000 Design Manual

General Purpose SPI Interface Design Guidelines—Intel
Table 36. SPI0_MISO
Trace Spacing(S3): Between GPIO
and other signals
Trace Segment Length
Note: * Keep Lc + Ld as short as possible to give the best margin on the overshoot/undershoot violation.
Data to Clock MB length matching rule
Number of vias
Rs
Reference Plane
Buffer
1. This requirement relates to the platform routing and does not include the inter package routing.
Note: The guidelines regarding the routing of the GPIO based CS are TBD.
Figure 34.

SPI1 Topology

Table 37. SPI1_MOSI, SPI1_SCK
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
GPIO Signals
Trace Spacing(S3): Between
GPIO and other signals
Trace Segment Length
June 2014
Order Number: 330258-002US
SoC
Breakout
L
A
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
0.5"
®
Quark™ SoC X1000
Breakout
4.2 mil 10 mil
0.5" max 0.1" - 3.0"
1
Connector
Rs
L L
B C
Breakout
4 Layer
L
B
MS
50 Ω +/- 15%
4.2 mil
10 mil
15 mil
min = 0.2"
max = 0.8"
10 mil 4.2 mil
0.1" - 0.8" 0.5" max
< 200mils
max 2
33ohm +/- 5%
Solid Ground Reference
c69p0cfiohvtewtop_3.3V_po
lo
J11
SPI SLave
L
D
4 Layer 4 Layer
L L
C D
MS MS
4.2 mil 4.2 mil
10 mil 10 mil
15 mil 15 mil
min = 0.1"
0.25" max
max = 1.5"
®
Intel Quark™ SoC X1000
PDG
69