I2C* Additional Guidelines; Terminating Unused I C Signals; Bus Capacitance Reference Chart; Example Bus Capacitance/Pull-Up Resistor Relationship - Intel Quark SoC X1000 Design Manual

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6.5 I C* Additional Guidelines
System designers must consider the total bus capacitance, which includes both SoC
and device pin capacitance and board trace length capacitance when designing I
The total bus capacitance must not exceed 400 pF.
info to help determine total bus capacitance and proper pull-up resistors on the I
buses. Analysis of a particular layout is still required to confirm correct operation.
Table 26.

Bus Capacitance Reference Chart

Device
MCP
Board Trace per
Inch
Table 27.

Example Bus Capacitance/Pull-Up Resistor Relationship

Physical Bus
Segment
Capacitance
10 to 50 pF
50 to 100 pF
10 to 100 pF
100 to 200 pF
200 to 300 pF
300 to 400 pF
6.6 Terminating Unused I
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If I C interfaces are not used, the signals should be terminated with external pull-up or
pull-down resistors.
®
Intel Quark™ SoC X1000
PDG
58
®
Intel
Capacitance Includes
Pin Capacitance
TBD pF per inch of trace length
Pull-Up Range
(For Vcc = 3.3 V)
100kHz
NA
NA
9 k to 1 k
5 k to 1 k
3.5 k to 1 k
2.5 k to 1 k
2
C Signals
Quark™ SoC X1000—I2C* Interface Design Guidelines
Table 26 and
pF
pF
Pull-Up Range
(For Vcc = 3.3 V)
400kHz
NA
NA
2.4k to 0.4 k
1.6 k to 0.4 k
1 k to 0.4 k
0.8 k to 0.4 k
§ §
Order Number: 330258-002US
2
C bus.
Table 27 below provide
2
C
Units Capacitance
10
TBD
June 2014