Rmii Interface; Rmii Interface Signals; Rmii Reference Clock; Mdio Interface - Intel Quark SoC X1000 Design Manual

LAN Design Considerations and Guidelines—Intel
21.1.2

RMII Interface

21.1.2.1

RMII Interface Signals

The signals used to connect between the SoC and the PHY in this mode are:
• Two receive data bits running at 10/100 Mb/s for Rx.
• Two transmit data bits running at 10/100 Mb/s for Tx.
• 50 MHz reference clock input to the PHY is generated by the SOC.
• Transmit enable indicator from SOC to PHY.
• Receive data valid from PHY to SOc with receive data.
The PHY transmit/receive pins are output/input signals and are connected to the SOC
as listed in
21.1.2.2

RMII Reference Clock

The RMII Interface uses a 50 MHz reference clock, denoted RMII_REF_CLK. This signal
is generated from the SoC and routed to the PHY port and in to the MAC port reference
clock.
The frequency tolerance for the RMII reference clock is ±50 ppm.
21.1.3

MDIO Interface

MDIO is a low speed (2.5 MHz) serial bus used to connect various components in a
system. MDIO is used as an interface to pass management and configuration messages
between the PHY and the SOC
The MDIO uses two primary signals: MDC and MDIO, to communicate. MDC is pulled up
with a 4.7k resistor and MDIO is pulled up with a 1.5k resistor.
21.1.3.1

MDIO Connectivity

Table 64
MDIO pins.
Note: The MDIO signals (MDIO and MDC) cannot be connected to any other devices other
than the integrated MAC. Connect the MDIO and MDC pins to the integrated MAC0/1
MDIO and MDC pins, respectively.
21.2

Platform LAN Design Guidelines

These sections provide recommendations for selecting components and connecting
special pins. For Ethernet designs, the main elements are Intel
PHYs, a magnetics modules, RJ-45 connectors and a clock source.
21.2.1

General Design Considerations for PHYs

Sound engineering practices must be followed with respect to unused inputs by
terminating them with pull-up or pull-down resistors, unless otherwise specified in a
datasheet, design guide or reference schematic. Pull-up or pull-down resistors must not
be attached to any balls identified as "No Connect." These devices might have special
test modes that could be entered unintentionally.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Table 64 through Table
through Table 66 list the relationship between PHY MDIO pins to the SoC LAN
66.
®
Quark™ SoC X1000,
®
Intel Quark™ SoC X1000
PDG
147