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Intel Quark SoC X1000 Core Developer's Manual

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Intel
Quark SoC X1000 Core
Developer's Manual
October 2013
Order Number: 329679-001US

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Summary of Contents for Intel Quark SoC X1000 Core

  • Page 1 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 2 MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND...

  • Page 3: Revision History

    ® Revision History—Intel Quark Core Revision History Date Revision Description September 2013 First external release of document. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 4: Table Of Contents

    Contents About this Manual .......................17 Manual Contents....................17 Notation Conventions ..................18 Special Terminology ...................19 Related Documents ....................20 ® Intel Quark SoC X1000 Core Overview.................21 ® Intel Quark Core Architecture ................21 Architectural Overview....................22 Internal Architecture ..................22 System Architecture...................22 Memory Organization ..................22 3.3.1 Address Spaces ..................23...
  • Page 5 Selector Privilege (RPL) ............. 82 6.3.3.3 I/O Privilege and I/O Permission Bitmap ........83 6.3.3.4 Privilege Validation..............85 6.3.3.5 Descriptor Access ..............85 6.3.4 Privilege Level Transfers................86 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 6 7.7.1 Write-Back Enhanced Intel Quark SoC X1000 Core Cache Flushing .... 122 ® Write-Back Enhanced Intel Quark SoC X1000 Core Write-Back Cache Architecture . 123 7.8.1 Write-Back Cache Coherency Protocol............123 ® 7.8.2 Detecting On-Chip Write-Back Cache of the Write-Back Enhanced Intel Quark SoC X1000 Core................
  • Page 7 Entering System Management Mode ............134 8.4.2 Processor Environment................135 ® 8.4.2.1 Write-Back Enhanced Intel Quark SoC X1000 Core Environment . 136 8.4.3 Executing System Management Mode Handler.......... 136 8.4.3.1 Exceptions and Interrupts within System Management Mode ..137 SMM Features ....................138 8.5.1...
  • Page 8 9.2.15 Bus Size Control (BS16#, BS8#) ............160 9.2.16 Address Bit 20 Mask (A20M#) ..............161 ® 9.2.17 Write-Back Enhanced Intel Quark SoC X1000 Core Signals and Other Enhanced Bus Features ................. 161 9.2.17.1 Cacheability (CACHE#) ............161 9.2.17.2 Cache Flush (FLUSH#) ............. 162 9.2.17.3 Hit/Miss to a Modified Line (HITM#) ...........
  • Page 9 ® Contents—Intel Quark Core ® 9.6.3 Write-Back Enhanced Intel Quark SoC X1000 Core Pin States During Stop Grant State ..................176 9.6.4 Clock Control State Diagram ..............177 9.6.4.1 Normal State................177 9.6.4.2 Stop Grant State ..............177 9.6.4.3 Stop Clock State ..............179 9.6.4.4...
  • Page 10 10.3.14Floating-Point Error Handling for the Intel Quark SoC X1000 Core ..... 225 10.3.14.1Floating-Point Exceptions ............225 ® 10.3.15Intel Quark SoC X1000 Core Floating-Point Error Handling in AT-Compatible Systems................. 226 ® 10.4 Enhanced Bus Mode Operation for the Write-Back Enhanced Intel Quark SoC X1000 Core ......................
  • Page 11 Cache Testability Write ................. 297 B.1.3 Cache Testability Read ................298 B.1.4 Flush Cache..................299 ® B.1.5 Additional Cache Testing Features for Write-Back Enhanced Intel Quark SoC X1000 Core................... 299 Translation Lookaside Buffer (TLB) Testing ............300 B.2.1 Translation Lookaside Buffer Organization..........300 B.2.2 TLB Test Registers TR6 and TR7 .............
  • Page 12 ® Intel Quark Core—Contents Base Architecture Registers ..................40 Flag Registers ......................41 ® Intel Quark SoC X1000 Core Segment Registers and Associated Descriptor Cache Registers.........................45 System-Level Registers .....................46 Control Registers .....................47 ® Intel Quark SoC X1000 Core CR4 Register ..............52 Floating-Point Registers.....................53 Floating-Point Tag Word ....................54...
  • Page 13 Pin States During RESET ..................172 Stop Clock Protocol ....................175 ® Intel Quark SoC X1000 Core Stop Clock State Machine ..........178 Recognition of Inputs when Exiting Stop Grant State ..........179 ® Write-Back Enhanced Intel Quark SoC X1000 Core Stop Clock State Machine (Enhanced Bus Configuration) ....................
  • Page 14 127 Size Breakpoint Fields ..................... 248 128 General Instruction Format ..................253 ® 129 Intel Quark SoC X1000 Core Cache Test Registers ............ 296 130 TR4 Definition for Standard and Enhanced Bus Modes for the Write-Back Enhanced ® Intel Quark SoC X1000 Core .................. 300 131 TR5 Definition for Standard and Enhanced Bus Modes for the Write-Back Enhanced ®...
  • Page 15 Pin State during Stop Grant Bus State ..............175 ® Write-Back Enhanced Intel Quark SoC X1000 Core Pin States during Stop Grant Bus Cycle........................176 Byte Enables and Associated Data and Operand Bytes..........184 Generating A[31:0] from BE[3:0]# and A[31:A2]............185 Next Byte Enable Values for BSx# Cycles ..............
  • Page 16 I/O Instructions Clock Count Summary..............281 Floating-Point Clock Count Summary................. 283 ® Intel Quark SoC X1000 Core Pin Descriptions ............291 Cache Control Bit Encoding and Effect of Control Bits on Entry Select and Set Select Functionality ......................298 ®...

  • Page 17: About This Manual

    Describes Protected Mode, including segmentation, protection, and paging. Mode Architecture” ® Chapter 7.0, “On-Chip The Intel Quark SoC X1000 Core contains an on-chip cache, also known as L1 Cache” cache. This chapter describes its functionality. ® Chapter 8.0, “System Describes the System Management Mode architecture of the Intel...

  • Page 18: Notation Conventions

    Quark SoC X1000 Core, including on-chip Appendix B, “Testability” cache testing, translation lookaside buffer (TLB) testing, and JTAG. ® Appendix C, “Feature Documents the CPUID function, which is used to determine the Intel Quark SoC Determination” X1000 Core identification and processor-specific information. Notation Conventions The following notations are used throughout this manual.

  • Page 19: Special Terminology

    If a bit is set, its value is “1”; setting a bit gives it a “1” value. If a bit is clear, its value is “0”; clearing a bit gives it a “0” value. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 20: Related Documents

    ® Intel Quark Core—About this Manual Related Documents The following Intel documents contain additional information on designing systems that ® incorporate the Intel Quark SoC X1000 Core. Table 2. Related Documents Ref. Document Name Order Number ® [HRM] Intel Quark SoC X1000 Core Hardware Reference Manual 329678 ®...

  • Page 21: Intel Quark Soc X1000 Core Overview

    Quark SoC X1000 Core Overview ® The Intel Quark Core enables a range of low-cost, high-performance embedded system designs capable of running applications written for the Intel architecture. The ® Intel Quark Core integrates a 16-Kbyte unified cache and floating-point hardware on- ®...

  • Page 22: Architectural Overview

    ® Memory on the Intel Quark SoC X1000 Core is divided up into 8-bit quantities (bytes), 16-bit quantities (words), and 32-bit quantities (dwords). Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address, the high order byte at the high address.

  • Page 23: Address Spaces

    ® The Intel Quark SoC X1000 Core supports both pages and segments in order to provide maximum flexibility to the system designer. Segmentation and paging are complementary. Segmentation is useful for organizing memory in logical modules, and as such is a tool for the application programmer, while pages are useful for the system programmer for managing the physical memory of a system.

  • Page 24: Segment Register Usage

    3.3.2 Segment Register Usage ® The main data structure used to organize memory is the segment. On the Intel Quark SoC X1000 Core, segments are variable sized blocks of linear addresses which have certain attributes associated with them. There are two main types of segments: code and data.

  • Page 25: I/O Space

    Quark Core I/O Space ® The Intel Quark SoC X1000 Core allows 64 K+3 bytes to be addressed within the I/O ® space. The Host Bridge propagates the Intel Quark SoC X1000 Core I/O address without any translation on to the destination bus and, therefore, provides addressability for 64 K+3 byte locations.

  • Page 26: Register And Immediate Modes

    Based Index Mode: The contents of a BASE register is added to the contents of an INDEX register to form the effective address of an operand. Example: MOV EAX, [ESI] [EBX] ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 27: Addressing Mode Calculations

    SCALING factor, the result is added to the contents of a BASE register and a DISPLACEMENT to form the operand’s offset. Example: MOV EAX, LOCALTABLE[EDI*4] [EBP+80] ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 28: Differences Between 16- And 32-Bit Addresses

    0, 8, 32 bits Data Types 3.6.1 Data Types ® The Intel Quark SoC X1000 Core can support a wide-variety of data types. In the following descriptions, the processor consists of the base architecture registers. ® Intel Quark SoC X1000 Core Developer’s Manual...

  • Page 29: Unsigned Data Types

    The number is negative if the sign bit is 1. If the sign bit is 0, the number is positive. The magnitude field consists of the remaining bits in the number. (Refer to Figure ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 30: Bcd Data Types

    A string data type is a contiguous sequence of bits, bytes, words or dwords. A string may contain between 1 byte and 4 Gbytes. (Refer to Figure ® String data types are only supported by the CPU section of the Intel Quark SoC X1000 Core. Byte String: Contiguous sequence of bytes.

  • Page 31: Ascii Data Types

    3.6.1.6 ASCII Data Types ® The Intel Quark SoC X1000 Core supports ASCII (American Standard Code for Information Interchange) strings and can perform arithmetic operations (such as ® addition and division) on ASCII data. The Intel Quark SoC X1000 Core can only operate on ASCII data;...

  • Page 32: Pointer Data Types

    3.6.1.7 Pointer Data Types ® A pointer data type contains a value that gives the address of a piece of data. Intel Quark SoC X1000 Core support the following two types of pointers (see Figure • 48-bit Pointer: 16-bit selector and 32-bit offset •...

  • Page 33: Little Endian Vs. Big Endian Data Formats

    ® The Intel Quark SoC X1000 Core, as well as all other members of the Intel architecture, use the “little-endian” method for storing data types that are larger than one byte. Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address and the high order byte at the high address.

  • Page 34: Interrupt Processing

    8-byte quantities, which are put in an Interrupt Descriptor Table (see Section 6.2.3.4, “Interrupt Descriptor Table” on page 71). Of the 256 possible interrupts, 32 are reserved for use by Intel, the remaining 224 are free to be used by the system designer. 3.7.2 Interrupt Processing When an interrupt occurs, the following actions happen.

  • Page 35: Non-Maskable Interrupt

    2. Unlike a normal hardware interrupt, no interrupt acknowledgment sequence is performed for an NMI. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 36: Software Interrupts

    STPCLK# will be recognized while in an interrupt service routine or an SMM handler. ® Exceptions are internally-generated events. Exceptions are detected by the Intel ® Quark SoC X1000 Core if, in the course of executing an instruction, the Intel Quark ® SoC X1000 Core detects a problematic condition. The Intel Quark SoC X1000 Core then immediately invokes the appropriate exception service routine.

  • Page 37: Instruction Restart

    ® The Intel Quark SoC X1000 Core is in a state that permits restart of the instruction, for all cases except the following. An instruction causes a task switch to a task whose Task State Segment is partially “not present.” (An entirely “not present” TSS is restartable.) Partially present TSSs can be avoided either by keeping the TSSs of such...

  • Page 38: Double Fault

    Page Fault (exception 14). ® A Double Fault (exception 8) will also be generated when the Intel Quark SoC X1000 Core attempts to invoke the Page Fault (exception 14) service routine, and detects an exception other than a second Page Fault.

  • Page 39: System Register Organization

    System Register Organization—Intel Quark Core System Register Organization Register Set Overview ® The Intel Quark SoC X1000 Core register set can be split into the following categories: • Base Architecture Registers — General Purpose Registers — Instruction Pointer — Flags Register —...

  • Page 40: General Purpose Registers

    16 and 32 bits, and bit fields of 1 to 32 bits. Address operands of 16 and 32 bits are supported. The 32-bit registers are named EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 41: Instruction Pointer

    Figure 10 shows the EFLAGS register. EFLAGS bits 1, 3, 5, 15, and 22 to 31 are defined as “Intel Reserved.” When these bits are stored during interrupt processing or with a PUSHF instruction (push flags onto stack), a “1” is stored in bit 1 and zeros are stored in bits 3, 5, 15, and 22 to 31.

  • Page 42: Data Type Alignment Requirements

    Quark SoC X1000 Core generate misaligned ® references, even when their memory address is aligned. For example, on the Intel Quark SoC X1000 Core, the SGDT/SIDT (store global/interrupt descriptor table) instruction reads/writes two bytes, and then reads/writes four bytes from a “pseudo- ®...
  • Page 43 ® ® set while the Intel Quark SoC X1000 Core is in Protected Mode, the Intel Quark SoC X1000 Core switches to Virtual 8086 operation, handling segment loads and generating exception 13 faults on privileged opcodes. The VM bit can be set only in Protected Mode by the IRET instruction (when current privilege level = 0) and by task switches at any privilege level.

  • Page 44: Segment Registers

    TF controls the generation of the exception 1 trap when the processor is single- ® stepping through code. When TF is set, the Intel Quark SoC X1000 Core generates an exception 1 trap after the next instruction is executed. When TF is reset, exception 1 traps occur only as a function of the breakpoint addresses loaded into debug registers DR[3:0].

  • Page 45: System-Level Registers

    The system-level registers include three control registers and four segmentation base registers. The three control registers are CR0, CR2 and CR3. CR1 is reserved for future Intel processors. The four segmentation base registers are the Global Descriptor Table Register (GDTR), the Interrupt Descriptor Table Register (IDTR), the Local Descriptor Table Register (LDTR) and the Task State Segment Register (TR).

  • Page 46: Control Registers

    Section 4.4.1.3, “Control Register 2 (CR2)” on page 51 • Section 4.4.1.4, “Control Register 3 (CR3)” on page 51 • Section 4.4.1.5, “Control Register 4 (CR4)” on page 51 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 47: Control Register 0 (Cr0)

    13, contains 10 bits for control and status purposes. The function of the bits in CR0 can be categorized as follows: ® • Intel Quark SoC X1000 Core Operating Modes: PG, PE (Table • On-Chip Cache Control Modes: CD, NW (Table •...

  • Page 48: Intel ® Quark Soc X1000 Core Operating Modes

    LMSW and SMSW instructions in the Intel Quark SoC X1000 Core operate only on the ® low-order 16 bits of CR0 and ignore the new bits. New Intel Quark SoC X1000 Core operating systems should use the MOV CR0, Reg instruction.
  • Page 49 The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR# pin are used with external logic to implement PC-style error reporting.

  • Page 50: Recommended Values Of The Floating-Point Related Bits For Intel

    Exception 7 Execute ® Note: For Intel Quark SoC X1000 Core, when MP=1 and TS=1, the processor generates a trap 7 so that the system software can save the floating-point status of the old task. ® Intel Quark SoC X1000 Core Developer’s Manual...

  • Page 51: Control Register 1 (Cr1)

    Exception 7 ® Note: For Intel Quark SoC X1000 Core, when MP=1 and TS=1, the processor generates a trap 7 so that the system software can save the floating-point status of the old task. 4.4.1.2 Control Register 1 (CR1) CR1 is reserved for use in future Intel processors.

  • Page 52: System Address Registers

    Four special registers are defined to reference the tables or segments supported by the ® Intel Quark SoC X1000 Core protection model. These tables or segments are: GDT (Global Descriptor Table), IDT (Interrupt Descriptor Table), LDT (Local Descriptor Table), TSS (Task State Segment).

  • Page 53: Floating-Point Registers

    A “pop” operation stores the value from the current top register ® and then increments TOP by one. Like other Intel Quark SoC X1000 Core stacks in memory, the FPU register stack grows “down” toward lower-addressed registers.

  • Page 54: Floating-Point Tag Word

    Floating-Point Status Word The 16-bit status word reflects the overall state of the FPU. The status word is shown in Figure 17 and is located in the status register. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 55: Floating-Point Status Word

    C0-C3 to reflect the outcome. The effects of these instructions on the condition codes are summarized in Table 4-7 through Table 4-10. A5152-01 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 56: Condition Code Interpretation After Fprem And Fprem1 Instructions

    Roundup: When the PE bit of the status word is set, this bit indicates whether the last rounding in the instruction was upward. UNDEFINED: Do not rely on finding any specific value in these bits. See Section 4.8, “Reserved Bits and Software Compatibility” on page ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 57: Condition Code Resulting From Comparison

    ES bit in the status word is ® set, and the FERR# output signal is asserted. When the Intel Quark SoC X1000 Core attempts to execute another floating-point or WAIT instruction, exception 16 occurs or an external interrupt happens if the NE=1 in control register 0.

  • Page 58: Instruction And Data Pointers

    FSAVE (save state) and FRSTOR (restore state) instructions. Whenever ® the Intel Quark SoC X1000 Core decodes a new floating-point instruction, it saves the instruction (including any prefixes that may be present), the address of the operand (if present) and the opcode.

  • Page 59: Protected Mode Fpu Instructions And Data Pointer Image In Memory (32-Bit Format)

    Status Word Intel Reserved Tag Word Intel Reserved Instruction Pointer 15..0 0000 Instruction Pointer 31..16 OPCODE 10..0 Intel Reserved Operand Pointer 15..0 0000 Operand 31..16 0000 00000000 A5154-01 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 60: Protected Mode Fpu Instruction And Data Pointer Image In Memory (16-Bit Format)

    Control Word Status Word Tag Word Instruction Pointer 15..0 IP19.16 OPCODE 10..0 Operand Pointer 15..0 DP19.16 0 0 0 0 0 0 0 0 0 0 0 A5156-01 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 61: Fpu Control Word

    PC bits can be used to set the FPU internal operating precision of the significand at less than the default of 64 bits (extended precision). This can be useful in providing compatibility with early generation arithmetic processors of smaller precision. PC ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 62: Debug And Test Registers

    4.6.2 Test Registers ® The Intel Quark SoC X1000 Core contains the test registers listed in Table 20. TR6 and TR7 are used to control the testing of the translation lookaside buffer. TR3, TR4 and TR5 are used for testing the on-chip cache. The use of the test registers is discussed in Appendix B, “Testability.”...

  • Page 63: Fpu Register Usage

    Mask out the reserved bits when testing. • Do not depend on the states of any reserved bits when storing to memory or another register. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 64: Intel ® Quark Core Model Specific Registers (Msrs)

    ® Note: Avoid any software dependence upon the state of reserved bits in Intel Quark SoC X1000 Core registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits.

  • Page 65: Real Mode Architecture

    Real Mode Architecture Introduction ® When the Intel Quark SoC X1000 Core is powered up or reset, it is initialized in Real ® Mode. Real Mode allows access to the 32-bit register set of the Intel Quark SoC X1000 Core.

  • Page 66: Memory Addressing

    ® executed. The Intel Quark SoC X1000 Core generates an exception 13 if a data operand or instruction fetch occurs past the end of a segment (i.e., if an operand has an offset greater than FFFFH, as when a word has a low byte at FFFFH and the high byte at 0000H).

  • Page 67: Interrupts

    X1000 Core from using the local bus until restarted via the RESUME instruction. The ® Intel Quark SoC X1000 Core is forced out of halt by NMI, INTR with interrupts enabled (IF=1), or by RESET. If interrupted, the saved CS:IP points to the next instruction after the HLT.

  • Page 68: Protected Mode Architecture

    Protected Mode. Paging provides a means of managing the very large segments of the ® Intel Quark SoC X1000 Core. As such, paging operates beneath segmentation. The paging mechanism translates the protected linear address that comes from the ® segmentation unit into a physical address.

  • Page 69: Segmentation

    8-byte data structure called a descriptor. All of the descriptors in a system are contained in tables recognized by hardware. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 70: Terminology

    6.2.3 Descriptor Tables 6.2.3.1 Descriptor Tables Introduction ® The descriptor tables define all of the segments that are used in a Intel Quark SoC ® X1000 Core system (see Figure 26). There are three types of tables on the Intel Quark SoC X1000 Core that hold descriptors: the Global Descriptor Table, Local Descriptor Table, and the Interrupt Descriptor Table.

  • Page 71: Global Descriptor Table

    The IDT should be at least 256 bytes in order to hold the descriptors for the 32 Intel Reserved Interrupts. Every interrupt used by a system must have an entry in the IDT. The IDT entries are referenced via INT instructions, external interrupt vectors, and exceptions (see Section 3.7, “Interrupts”...

  • Page 72: Descriptors

    ® The Intel Quark SoC X1000 Core has two main categories of segments: system segments and non-system segments (for code and data). The S bit in the segment descriptor determines if a given segment is a system segment or a code or data segment.

  • Page 73: Segment Descriptors

    Quark Core ® granularity is unrelated to paging. A Intel Quark SoC X1000 Core system can consist of segments with byte granularity and page granularity, whether or not paging is enabled. The executable (E) bit tells if a segment is a code or data segment. A code segment (E=1, S=1) may be execute-only or execute/read as determined by the Read (R) bit.

  • Page 74: System Descriptor Formats

    ® Segments identified as data segments (E=0, S=1) are used for two types of Intel Quark SoC X1000 Core segments: stack and data segments. The expansion direction (ED) bit specifies if a segment expands downward (stack) or upward (data). If a segment is a stack segment, all offsets must be greater than the segment limit.

  • Page 75: Ldt Descriptors (S=0, Type=2)

    Undefined (Intel Reserved) ® Busy Intel Quark SoC X1000 Busy 80286 TSS Core TSS ® Intel Quark SoC X1000 Core call 80286 call gate gate ® Task Gate (for 80286, Intel Quark SoC X1000 Undefined (Intel Reserved) Core task) ®...

  • Page 76: Gate Descriptor Formats

    DPL—least privileged level at which a task may access the gate. WORD COUNT 0–31—the number of parameters to copy from caller's stack to the called procedure's stack. The parameters are 32-bit quan- ® tities for Intel Quark SoC X1000 Core gates, and 16-bit quantities for 80286 gates. DESTINATION 16-bit Selector to the target code segment...

  • Page 77: Selector Fields

    The contents of the segment descriptor cache vary depending on the mode in which the ® Intel Quark SoC X1000 Core is operating. When operating in Real Address Mode, the segment base, limit, and other attributes within the segment cache registers are defined as shown in Figure 32.

  • Page 78: Example Descriptor Selection

    Selector Segment Register - - - - Index Table Indicator TI = 1 TI = 0 Descriptor Number Descriptor Null Local Descriptor Global Descriptor Table Table A5213-01 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 79: Segment Descriptor Caches For Real Address Mode

    The virtual program executes at lowest privilege level, level 3, to allow trapping of all IOPL-sensitive instructions and level-0-only instructions. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 80: Segment Descriptor Caches For Protected Mode (Loaded Per Descriptor)

    = per segment descriptor, but descriptor must indicate “writeable” to avoid exception 13 (special case for SS) – = does not apply to that segment cache register ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 81: Protection

    ® The Intel Quark SoC X1000 Core has four levels of protection that support multi- tasking by isolating and protecting user programs from each other and the operating system. The privilege levels control the use of privileged instructions, I/O instructions, and access to segments and segment descriptors.

  • Page 82: Rules Of Privilege

    ® The Intel Quark SoC X1000 Core controls access to both data and procedures between levels of a task, according to the following rules. • Data stored in a segment with privilege level p can be accessed only by code executing at a privilege level at least as privileged as p.

  • Page 83: I/O Privilege And I/O Permission Bitmap

    IN, OUT, INS, OUTS, REP INS, and REP OUTS.) When CPL > IOPL and the current task is associated with a 286 TSS, attempted I/O instructions cause an exception 13 ® fault. When CPL > IOPL and the current task is associated with a Intel Quark SoC ®...

  • Page 84: Intel ® Quark Core Tss And Tss Registers

    ® Intel Quark Core—Protected Mode Architecture ® Figure 36. Intel Quark Core TSS and TSS Registers ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 85: Privilege Validation

    6.3.3.4 Privilege Validation ® The Intel Quark SoC X1000 Core provides several instructions to speed pointer testing and help maintain system integrity by verifying that the selector value refers to an appropriate segment. Table 27 summarizes the selector validation procedures ®...

  • Page 86: Privilege Level Transfers

    Intel Quark Core—Protected Mode Architecture ® Any time an instruction loads data segment registers (DS, ES, FS, GS) the Intel Quark SoC X1000 Core makes protection validation checks. Selectors loaded in the DS, ES, FS, GS registers must refer only to data segments or readable code segments. (The...

  • Page 87: Call Gates

    Call Gates are accessed via a CALL instruction and are syntactically identical to calling a ® normal subroutine. When an inter-level Intel Quark SoC X1000 Core call gate is activated, the following actions occur. 1. Load CS:EIP from gate check for validity.

  • Page 88: Task Switching

    Quark SoC X1000 Core TSS. The limit of an Intel Quark SoC X1000 Core TSS must be greater than 0064H and can be as large as 4 Gbytes. In the additional TSS space, the operating system is free to store additional information, such as the reason the task is inactive, the time the task has spent running, and the open files belonging to the task.

  • Page 89: Floating-Point Task Switching

    ® The Intel Quark SoC X1000 Core task state segment is marked busy by changing the descriptor type field from TYPE 9H to TYPE BH. Use of a selector that references a busy task state segment causes an exception 13.

  • Page 90: Simple Protected System

    Quark Core—Protected Mode Architecture ® a simple Protected Mode Intel Quark SoC X1000 Core system. It has a single code and single data/stack segment, each four-Gbytes long, and a single privilege level, PL = 0. The actual method of enabling Protected Mode is to load CR0 with the PE bit set via the MOV CR0, R/M instruction.

  • Page 91: Paging

    6.4.2.1 Page Mechanism ® The Intel Quark SoC X1000 Core uses two levels of tables to translate the linear address (from the segmentation unit) to a physical address. There are three ® components to the paging mechanism of the Intel Quark SoC X1000 Core: the page directory, the page tables, and the page itself (page frame).

  • Page 92: Page Directory

    31 bits could be used to indicate where on the disk the page is stored. ® Bit 5, the Accessed (A) bit, is set by the Intel Quark SoC X1000 Core for both types of entries before a read or write access occurs to an address covered by the entry. Bit 6, the D (Dirty) bit, is set to 1 before a write to an address covered by that page table entry occurs.

  • Page 93: Pae Paging

    MOV to CR instruction causes a general-protection exception (#GP(0)) and the PDPTEs are not loaded. As shown in Table 30, bits 2:1, 8:5, and 63:MAXPHYADDR are reserved in the PDPTEs. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 94: Linear-Address Translation With Pae Paging

    63:M Reserved (must be 0) ® † M is an abbreviation for MAXPHYADDR, which is set to 32 for Intel Quark SoC X1000 Core. 6.4.3.2 Linear-Address Translation with PAE Paging PAE paging may map linear addresses to either 4-KByte pages or 2-MByte pages.

  • Page 95: Linear-Address Translation To A 4-Kbyte Page Using Pae Paging

    • If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved. ® • If the PAT is not supported (as in Intel Quark SoC X1000 Core): — If the P flag of a PTE is 1, bit 7 is reserved.

  • Page 96: Linear-Address Translation To A 2-Mbyte Page Using Pae Paging

    8 (G) otherwise 11:9 Ignored ® 12 (PAT) Reserved for Intel Quark SoC X1000 Core (must be 0) 20:13 Reserved (must be 0) (M–1):21 Physical address of the 2-MByte page referenced by this entry 62:M Reserved (must be 0) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from 63 (XD) the 2-MByte page controlled by this entry);...

  • Page 97: Format Of A Pae Page-Directory Entry That References A

    Dirty; indicates whether software has written to the 4-KByte page referenced by 6 (D) this entry ® 7 (PAT) Reserved for Intel Quark SoC X1000 Core (must be 0) Global; if CR4.PGE = 1, determines whether the translation is global; ignored 8 (G) otherwise 11:9 Ignored (M–1):12...

  • Page 98: Formats Of Cr3 And Paging-Structure Entries In 32-Bit Mode With Pae Paging Disabled

    (PS) are highlighted because they determine how a paging-structure entry is used. Figure 43. Formats of CR3 and Paging-Structure Entries in 32-bit Mode with PAE Paging Disabled ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 99: Formats Of Cr3 And Paging-Structure Entries In 32-Bit Mode With Pae Paging Enabled

    ® Protected Mode Architecture—Intel Quark Core Figure 44. Formats of CR3 and Paging-Structure Entries in 32-bit Mode with PAE Paging Enabled ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 100: Quark Soc X1000 Core

    6.4.4 #GP Faults for Intel Quark SoC X1000 Core Failures to load the PDPTE registers with PAE paging causes #GP fault. • If any of the PDPTEs sets both the P flag (bit 0) and any reserved bit, it causes a general-protection exception (#GP(0)) and the PDPTEs are not loaded.

  • Page 101: Smep Details For Intel ® Quark Soc X1000 Core

    ® 6.4.5.1 SMEP Details for Intel Quark SoC X1000 Core • Functionality/implementation is same as Silvermont. • Enabled by setting CR4.SMEP (CR4[20])= 1. • In supervisor mode (CPL < 3), a #PF is caused by code fetch from a page whose mapping has the U/S bit set (CPL=3) at every level of the translation for the linear address.

  • Page 102: Page Level Protection (R/W, U/S Bits)

    Page Level Protection (R/W, U/S Bits) ® The Intel Quark SoC X1000 Core provides a set of protection attributes for paging systems. The paging mechanism distinguishes between two levels of protection: user, which corresponds to level 3 of the segmentation based protection; and supervisor, which encompasses all of the other protection levels (0, 1, 2).

  • Page 103: Page Cacheability (Pwt And Pcd Bits)

    Lookaside Buffer (TLB). The TLB is a four-way set associative 32-entry page table ® cache. It automatically keeps the most commonly used page table entries in the Intel Quark SoC X1000 Core. The 32-entry TLB coupled with a 4 Kbyte page size, results in coverage of 128 Kbytes of memory addresses. ®...

  • Page 104: Page-Fault Exceptions

    Again, note that the page table entry actually is read twice if the ® Intel Quark SoC X1000 Core needs to set any of the bits in the entry. Like the directory entry, if the data changes between the first and second read, the data returned for the second read is used.

  • Page 105: Page-Fault Error Code

    Software developers should be aware that such bits may be used in the future and that a paging-structure entry that causes a page-fault exception on one processor might not do so in the future. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 106: Paging Operation

    TLB for future accesses. ® However, if P = 0 for either the page directory entry or the page table entry, the Intel Quark SoC X1000 Core generates a page fault, exception 14.

  • Page 107: Operating System Responsibilities

    † Descriptor table access faults with U/S = 0, even if the program is executing at level 3. • U: UNDEFINED ® • U/S: The U/S bit indicates whether the access causing the fault occurred when the Intel Quark SoC X1000 Core was executing in User Mode (U/S = 1) or in Supervisor mode (U/S = 0).

  • Page 108: Virtual 8086 Mode Addressing Mechanism

    ® The Intel Quark SoC X1000 Core allows the operating system to specify which programs use Real Mode and which programs use Protected Mode addressing. Through the use of paging, the one megabyte address space of the Virtual Mode task can be ®...

  • Page 109: Protection And I/O Permission Bitmap

    Figure 48 shows how the ® Intel Quark SoC X1000 Core paging hardware enables multiple programs to run under a virtual memory demand paged system. 6.5.4 Protection and I/O Permission Bitmap All Virtual 8086 Mode programs execute at privilege level 3, the level of least privilege.

  • Page 110: Interrupt Handling

    Interrupt Handling Interrupts in Virtual 8086 Mode are handled in a unique way. When running in Virtual ® Mode, all interrupts and exceptions involve a privilege change back to the host Intel ® Quark SoC X1000 Core operating system. The Intel...

  • Page 111: Entering And Leaving Virtual 8086 Mode

    ® task with a Intel Quark SoC X1000 Core TSS that has a 1 in the VM bit in the EFLAGS image. The other way is to execute a 32-bit IRET instruction at privilege level 0, where the stack has a 1 in the VM bit in the EFLAGS image. POPF does not affect the VM bit, ®...

  • Page 112: Task Switches To And From Virtual 8086 Mode

    ® interrupt handler in protected Intel Quark SoC X1000 Core mode. That is, as part of interrupt processing, the VM bit is cleared. Because the matching IRET must occur from level 0, if an interrupt or trap gate is used to field an interrupt or exception out of Virtual 8086 Mode, the Gate must perform an inter-level interrupt only to level 0.
  • Page 113 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 114: On-Chip Cache

    Quark Core—On-Chip Cache On-Chip Cache ® The Intel Quark SoC X1000 Core processor has a 16-Kbyte cache, as discussed in Section 7.1.1. The cache is software-transparent to maintain binary compatibility with previous generations of the Intel Architecture. The on-chip cache is designed for maximum flexibility and performance. The cache has several operating modes, offering flexibility during program execution and debugging.

  • Page 115: Write-Back Enhanced Intel ® Quark Soc X1000 Core Cache

    Unless specifically noted, the following sections apply to the Write-Back Enhanced ® Intel Quark SoC X1000 Core in Standard Bus Mode (write-through cache). ® Table 35. Write-Back Enhanced Intel Quark SoC X1000 Core WB/WT# Initialization...

  • Page 116: Cache Control

    Control and Operating Modes ® The Write-Back Enhanced Intel Quark SoC X1000 Core retains the use of CR0.CD and CR0.NW when the 1,1 state forces a cache-off condition after RESET and the 0,0 state is the normal run state. Table 37 defines these control bits when the cache is enabled for write-back operation.

  • Page 117: Cache Line Fills

    ® Intel Quark SoC X1000 Core. Cache line fills are generated only for read misses. Write misses never cause a line in the internal cache to be allocated. When a cache hit occurs on a write, the line is updated. Cache line fills can be performed over 8- and 16-bit buses using the dynamic bus sizing feature.

  • Page 118: Cache Line Invalidations

    When the snooped line is in the Write-Back Enhanced Intel Quark SoC X1000 Core’s cache and the line contains the most recent information, the processor must schedule a write back of the data. Inquire cycles are driven with INV = ®...

  • Page 119: Page Cacheability

    ® The PWT bit controls the write policy for second-level caches used with the Intel Quark SoC X1000 Core. Setting PWT=1 defines a write-through policy for the current page while PWT=0 defines the possibility of write-back. The state of PWT is ignored ®...
  • Page 120 Intel Quark SoC X1000 Core whether the area is cacheable. The Intel Quark SoC X1000 Core initiates a cache line fill when PCD and KEN# indicate that the requested information is cacheable. The PCD bit is OR’ed with the CD (cache disable) bit in control register 0 to determine ®...

  • Page 121: Page Cacheability

    PWT. The PWT bit controls the write policy for the second-level caches used with the ® Write-Back Enhanced Intel Quark SoC X1000 Core. Setting PWT to 1 defines a write- through policy for the current page, while clearing PWT to 0 defines a write-back policy for the current page.

  • Page 122: Cache Flushing

    The first flush acknowledge cycle is driven by the Write-Back Enhanced ® Intel Quark SoC X1000 Core, followed by the second flush acknowledge cycle after all write-backs and invalidations are complete. The two special cycles are issued even when there are no dirty lines to write back.

  • Page 123: Write-Back Enhanced Intel

    Write-Back Enhanced ® Intel Quark SoC X1000 Core to execute a line fill (i.e., fetch the whole line into the cache from main memory). A write to an ® invalid line causes the Write-Back Enhanced Intel Quark SoC X1000 Core to execute a write-through cycle on the bus.

  • Page 124: Cache State Transitions For Write-Back Enhanced Intel Core-Initiated Unlocked Read Cycles

    State transitions are caused by processor-generated transactions (memory reads/writes) and by a set of external input signals and internally-generated variables. ® The Write-Back Enhanced Intel Quark SoC X1000 Core also drives certain pins as a consequence of the cache consistency protocol. Read Cycles Table 39 shows the state transitions for lines in the cache during unlocked read cycles.

  • Page 125: Detecting On-Chip Write-Back Cache Of The Write-Back Enhanced Intel Quark Soc X1000 Core

    Write-Back Enhanced Intel Quark SoC X1000 Core. Snoop cycles may be initiated with or without an invalidation request (INV = 1 or 0). When a snoop cycle is initiated with INV = 0 (usually during memory read cycles by another master), it is referred to as an inquire cycle.
  • Page 126 EAX register, EAX[7:4]. When the model number ® returned is 7 (identifying the presence of a Write-Back Enhanced Intel Quark SoC X1000 Core) and the family number is 4, the on-chip cache supports the write-back policy.

  • Page 127: System Management Mode (Smm) Architectures

    SMM Overview ® The Intel Quark SoC X1000 Core supports four modes: Real, Virtual-86, Protected, and System Management Mode (SMM). As an operating mode, SMM has a distinct processor environment, interface and hardware/software features. SMM provides system designers with a means of adding new software-controlled features to computer products that operate transparently to the operating system and software applications.

  • Page 128: System Management Interrupt Processing

    Note: The above sequence is valid for the default SMBASE value only. See the following sections for a description of the SMBASE register and SMBASE relocation. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 129: System Management Interrupt (Smi#)

    ® System Management Mode (SMM) Architectures—Intel Quark Core The System Management Interrupt hardware interface consists of the SMI# interrupt request input and the SMIACT# output the system uses to decode the SMRAM. Figure 54. Basic SMI# Hardware Interface SMI Interface 8.3.1...

  • Page 130: Smram

    ® The Intel Quark SoC X1000 Core uses the SMRAM space for state save and state restore operations during an SMI# and RSM. The SMI# handler, which also resides in SMRAM, uses the SMRAM space to store code, data and stacks. In addition, the SMI#...

  • Page 131: Smram State Save Map

    ® System Management Mode (SMM) Architectures—Intel Quark Core The processor asserts the SMIACT# output to indicate to the memory controller that it is operating in System Management Mode. The system logic should ensure that only the processor has access to this area. Alternate bus masters or DMA devices that try to access the SMRAM space when SMIACT# is active should be directed to system RAM in the respective area.

  • Page 132: Redirecting System Memory Addresses To Smram

    Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address and the high-order byte at the high address. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 133: Exit From Smm

    ® System Management Mode (SMM) Architectures—Intel Quark Core Table 42. SMRAM State Save Map (Sheet 2 of 2) Register Offset Register Writeable? 7FE0 7FDC 7FD8 7FD4 7FD0 7FCC 7FC8 7FC4 7FC0 LDTR 7FBC 7FB8 7FB4 7FB0 7FAC 7FA8 7FA7–7F98 Reserved...

  • Page 134: System Management Mode Programming Model

    SMM is one of the major operating modes, on a level with Protected Mode, Real Mode or Virtual-86 Mode. Figure 58 shows how the processor can enter SMM from any of the three modes and then return. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 135: Processor Environment

    ® System Management Mode (SMM) Architectures—Intel Quark Core Figure 58. Transition to and from System Management Mode Real Mode Reset or RSM SMI# Reset or PE=1 PE=0 SMI# System Reset Protected Mode Management Mode VM=0 VM=1 SMI# Virtual - 86 Mode Note: Reset could occur by asserting the RESET or SRESET pin.

  • Page 136: Write-Back Enhanced Intel ® Quark Soc X1000 Core Environment

    Write-Back Enhanced Intel Quark SoC X1000 Core Environment ® When the Write-Back Enhanced Intel Quark SoC X1000 Core is in Enhanced Bus Mode, SMI# has greater priority than debug exceptions and external interrupts, except for FLUSH# and SRESET (see Section 3.7.6).

  • Page 137: Exceptions And Interrupts Within System Management Mode

    ® System Management Mode (SMM) Architectures—Intel Quark Core The EM bit is cleared so that no exceptions are generated. (If the SMM was entered from Protected Mode, the Real Mode interrupt and exception support is not available.) The SMI# handler should not use floating-point unit instructions until the FPU is properly detected (within the SMI# handler) and the exception support is initialized.

  • Page 138: Smm Features

    SMRAM base address (see Table 44). ® The Intel Quark SoC X1000 Core supports I/O trap restart and SMBASE relocation features. 8.5.2 Auto Halt Restart The Auto HALT restart slot at register offset (word location) 7F02H in SMRAM indicates to the SMM handler that the SMI# interrupted the processor during a HALT state (bit 0 of slot 7F02H is set to 1 if the previous instruction was a HALT).

  • Page 139: I/O Instruction Restart

    ® System Management Mode (SMM) Architectures—Intel Quark Core instruction is executed (see Figure 60 Table 45). Figure 60. Auto HALT Restart Register Offset Intel Reserved 7F02H Auto HALT Restart Table 45. Bit Values for Auto HALT Restart Value of Value of...

  • Page 140: Smm Base Relocation

    ® The Intel Quark SoC X1000 Core provides a control register, SMBASE. The address space used as SMRAM can be modified by changing the SMBASE register before exiting an SMI# handler routine. SMBASE can be changed to any 32-Kbyte aligned value (values that are not 32-Kbyte aligned cause the processor to enter the shutdown state when executing the RSM instruction).

  • Page 141: Smm System Design Considerations

    ® System Management Mode (SMM) Architectures—Intel Quark Core To change the SMRAM base address and SMM jump vector location, the SMM handler should modify the SMBASE slot. Upon executing an RSM instruction, the processor reads the SMBASE slot and stores it internally. Upon recognition of the next SMI# request, the processor uses the new SMBASE slot for the SMRAM dump and SMI# jump vector.

  • Page 142: Cache Flushes

    SMM code/data. In this case the cache should be empty before the first memory read cycle during SMM and before the first normal cycle after exiting SMM (see Figure 65). ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 143: Flush# Mechanism During Smm

    ® System Management Mode (SMM) Architectures—Intel Quark Core Figure 65. FLUSH# Mechanism during SMM SMI# Instr Instr Instr Instr Instr State Slave SMM Handler State Resume SMI# SMIACT# Flush cache Cache must Cache must be empty be empty A5237-01 The FLUSH# and KEN# signals can be used to ensure cache coherency when switching between normal and SMM modes.

  • Page 144: Write-Back Enhanced Intel Management Mode And Cache Flushing

    A5239-01 ® 8.6.2.1 Write-Back Enhanced Intel Quark SoC X1000 Core System Management Mode and Cache Flushing Regardless of the on-chip cache mode (i.e., write-through or write-back) it is recommended that SMRAM be non-overlaid. This provides the greatest freedom for caching both SMRAM and normal memory, provides a simplified memory controller design, and eliminates the performance penalty of flushing.

  • Page 145: Cache Flushing (Overlaid Smram)

    WT or WB WT or WB ® If SMI# and FLUSH# are asserted together, the Write-Back Enhanced Intel Quark SoC X1000 Core guarantees that FLUSH# is recognized first, followed by the SMI#. If the cache is configured in the write-back mode, the modified lines are written back to the normal user space, followed by the two special cycles.

  • Page 146: Snoop During Smm

    8088 processor. The A20M# pin ® on Intel Quark SoC X1000 Core provides this function. When A20M# is active, all external bus cycles drive A20M# low, and all internal cache accesses are performed with A20M# low.

  • Page 147: Smm And Second-Level Write Buffers

    ® Before the Intel Quark SoC X1000 Core enters SMM, it empties its internal write buffers. This is necessary so that the data in the write buffers is written to normal memory space, not SMM space. Once the processor is ready to begin writing an SMM state save to SMRAM, it asserts SMIACT#.

  • Page 148: Exception Handling

    16 Mbytes, the DS and ES registers are still initialized to 0000 0000H. We can still access data in SMRAM by using 32-bit displacement registers: esi,00FFxxxxH;64K segment ;immediately ;below 16 M ax,ds:[esi] ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 149: Hardware Interface

    ADS# active in the first clock, and RDY# and/or BRDY# are active in the last clock. Data is transferred to or from the ® Intel Quark SoC X1000 Core during a data cycle. A bus cycle contains one or more data cycles. ® Intel...

  • Page 150: Signal Descriptions

    Clock (CLK) CLK provides the fundamental timing and the internal operating frequency for the ® Intel Quark SoC X1000 Core. All external timing parameters are specified with respect to the rising edge of CLK. 9.2.2 Address Bus (A[31:2], BE[3:0]#) A[31:2] and BE[3:0]# form the address bus and provide physical memory and I/O port ®...

  • Page 151: Data Lines (D[31:0])

    Quark SoC X1000 Core. Even parity information must be driven ® back to the Intel Quark SoC X1000 Core on these pins with the same timing as read ® information to ensure that the correct parity check status is indicated by the Intel Quark SoC X1000 Core.

  • Page 152: Bus Cycle Definition

    Intel Quark SoC X1000 Core. At all other times, it is inactive (high). PCHK# is never floated. ® Driving PCHK# is the only effect that bad input parity has on the Intel Quark SoC ® X1000 Core. The Intel Quark SoC X1000 Core does not vector to a bus error interrupt when bad data parity is returned.

  • Page 153: Pseudo-Lock Output (Plock#)

    ® Intel Quark SoC X1000 Core data. RDY# is ignored when the bus is idle and at the end of the first clock of the bus cycle. Because RDY# is sampled during address hold, data can be returned to the processor when AHOLD is active.

  • Page 154: Burst Control

    Intel Quark SoC X1000 Core data in response to a write. BRDY# is ignored when the bus is idle and at the end of the first clock in a bus cycle.

  • Page 155: Soft Reset Input (Sreset)

    ® The Intel Quark SoC X1000 Core generates two locked interrupt acknowledge bus cycles in response to asserting the INTR pin. An 8-bit interrupt number is latched from an external interrupt controller at the end of the second interrupt acknowledge cycle.

  • Page 156: Non-Maskable Interrupt Request Input (Nmi)

    If the frequency is changed or stopped, the Intel Quark SoC X1000 Core does not return to the Stop Grant state until the CLK input has been running at a constant frequency for the time period necessary to stabilize the PLL (minimum of 1 ms).

  • Page 157: Bus Hold Acknowledge Output (Hlda)

    HOLD. The response to BOFF# differs from the response to HOLD in two ® ways: First, the bus is floated immediately in response to BOFF#, whereas the Intel Quark SoC X1000 Core completes the current bus cycle before floating its bus in ® response to HOLD. Second the Intel Quark SoC X1000 Core does not assert HLDA in response to BOFF#.

  • Page 158: Address Hold Request Input (Ahold)

    9.2.10.1 Address Hold Request Input (AHOLD) ® AHOLD is the address hold request. It allows another bus master access to the Intel Quark SoC X1000 Core address bus for performing an internal cache invalidation cycle. ® Asserting AHOLD forces the Intel Quark SoC X1000 Core to stop driving its address bus in the next clock.

  • Page 159: Page Cacheability (Pwt, Pcd)

    ® page basis. The Intel Quark SoC X1000 Core does not perform a cache fill to any page in which bit 4 of the page table entry is set. PWT corresponds to the write-back bit and can be used by an external cache to provide this functionality. PCD and PWT bits are assigned a value of zero during Real Mode and when paging is disabled.

  • Page 160: Ignore Numeric Error Input (Ignne#)

    IGNNE# pin via a register; the default value of the register is 1'b0. ® When IGNNE# is asserted and FERR# is still activated, Intel Quark SoC X1000 Core ignores numeric errors and continue executing non-control floating-point instructions.

  • Page 161: Address Bit 20 Mask (A20M#)

    20 before performing a lookup in the internal cache and before driving a ® memory cycle to the outside world. When A20M# is asserted, the Intel Quark SoC X1000 Core emulates the 1-Mbyte address wraparound. A20M# is active low and must be asserted only when the processor is in Real Mode.

  • Page 162: Cache Flush (Flush#)

    Due to the non-allocate on write policy, this includes both cacheable and non-cacheable writes. PCD distinguishes between the two, but CACHE# does not. ® This behavior is the same as the existing specification of the Intel Quark SoC X1000 Core in write- through mode.

  • Page 163: Soft Reset (Sreset)

    Quark Core Signals Pin Symbol Relation To This Signal EADS# EADS# determines when INV is sampled. A[31:4] The address of the snooped cache line is provided on these pins. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 164: Write-Back/Write-Through (Wb/Wt#)

    The processor's indication of write-back vs. write-through is from the PWT ® pin, in which function and timing are the same as in the Standard mode of the Intel Quark SoC X1000 Core. To define write-back or write-through configuration of a line, WB/WT# is sampled in the...

  • Page 165: Test Mode Select (Tms)

    Interrupt and Non-Maskable Interrupt Interface ® The Intel Quark SoC X1000 Core provides four asynchronous interrupt inputs: INTR (interrupt request), NMI (non-maskable interrupt), SMI# (system management interrupt) and STPCLK# (stop clock interrupt). This section describes the hardware interface between the instruction execution unit and the pins. For a description of the...

  • Page 166: Interrupt Logic

    ® The Intel Quark SoC X1000 Core contains a two-clock synchronizer on the interrupt line. An interrupt request reaches the internal instruction execution unit two clocks after the INTR pin is asserted if proper setup is provided to the first stage of the synchronizer.

  • Page 167: Stpclk# Logic

    Write Buffers ® The Intel Quark SoC X1000 Core contains four write buffers to enhance the performance of consecutive writes to memory. The buffers can be filled at a rate of one write per clock until all buffers are filled.

  • Page 168: Reordering Of A Reads With Write Buffers

    ® miss. Under these conditions, the Intel Quark SoC X1000 Core does not read from an external memory location that needs to be updated by one of the pending writes. Reordering of a read with the writes pending in the buffers can only occur once before all the buffers are emptied.

  • Page 169: Write Buffers And I/O Cycles

    ® The Intel Quark SoC X1000 Core has a built in self test (BIST) that can be run during reset. BIST is invoked when the AHOLD pin is asserted for one clock before and de- asserted one clock after RESET is de-asserted. RESET must be active for 15 clocks with or without BIST being enabled.

  • Page 170: Floating-Point Register Values

    ® The Intel Quark SoC X1000 Core starts executing instructions at location FFFFFFF0H after RESET. When the first Inter Segment Jump or Call is executed, address lines ® A[31:20] drop low for CS-relative memory cycles, and the Intel Quark SoC X1000 Core executes instructions only in the lower 1 Mbyte of physical memory.

  • Page 171: Pin State During Reset

    ® The Intel Quark SoC X1000 Core recognizes and can respond to HOLD, AHOLD, and BOFF# requests regardless of the state of RESET. Thus, even though the processor is in reset, it can float its bus in response to any of these requests.

  • Page 172: Pin States During Reset

    (Async) ADS# BREQ A31:4, NDEFINED MIO#, BLAST A3, A2, NDEFINED PLOCK D/C#, W/R#, PCHK# LOCK# D[31:0] HLDA SMIACT# WB/WT# CACHE# (10) HITM# See notes on next page. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 173: Controlling The Clk Signal In The Processor During Power On

    Intel Quark SoC X1000 Core. The information in this section reflects what Intel considers a good clock design. Intel strongly recommends that system designers ensure that a clock signal is not ®...

  • Page 174: Ferr# Pin State During Reset For Intel

    Power Down mode once RESET is de-asserted. Similarly for ® power-up resets, if the upgrade processor is not taken out of the system, the Intel Quark SoC X1000 Core three-states its outputs upon sensing the RESERVED# pin active and enters the Power Down Mode after the falling edge of RESET.

  • Page 175: Pin State During Stop Grant

    Table 58. Pin State during Stop Grant Bus State (Sheet 1 of 2) Signal Type State A[3:2] Previous state A[31:4] Previous state D[31:0] Floated BE[3:0]# Previous state ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 176: Grant State

    ® the Write-Back Enhanced Intel Quark SoC X1000 Core generates HLDA and three- states all output and input/output signals that are three-stated during the HOLD/HLDA state. After HOLD is de-asserted, all signals return to the state they were in prior to the HOLD/HLDA sequence.

  • Page 177: Clock Control State Diagram

    While in the Stop Grant state, the pull-up resistors on STPCLK#, CLKMUL (for the ® Intel Quark SoC X1000 Core) and RESERVED# are disabled internally. The system must continue to drive these inputs to the state they were in immediately before the processor entered the Stop Grant state. For minimum processor power consumption, all other input pins should be driven to their inactive level while the processor is in the Stop Grant state.

  • Page 178: Intel ® Quark Soc X1000 Core Stop Clock State Machine

    CLK after STPCLK# is de-asserted, the corresponding interrupt is serviced. The ® Intel Quark SoC X1000 Core requires INTR to be held active until the processor issues an interrupt acknowledge cycle in order to guarantee recognition (see Figure 75).

  • Page 179: Stop Clock State

    It then re-freezes the clock to the processor core and returns to the previous state. The processor does not generate a bus cycle when it returns to the previous state. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 180: Auto Idle Power Down State

    ® memory or I/O bus cycle read, the Intel Quark SoC X1000 Core reduces its core clock rate to equal that of the external CLK frequency without affecting performance. When RDY# or BRDY# is asserted, the processor returns to clocking the core at the specified multiplier of the external CLK frequency.

  • Page 181: Stop Grant State

    ® clock after STPCLK# is removed. (Note that the Write-Back Enhanced Intel Quark SoC X1000 Core requires that INTR be held active until the processor issues an interrupt acknowledge cycle in order to guarantee recognition).

  • Page 182: Stop Clock State

    9.6.5.3 Stop Clock State ® The Stop Clock state is the lowest power consumption mode of the Intel Quark SoC X1000 Core, because it allows removal of the external clock. It also has the longest latency for returning to normal state. The Stop Clock state is entered from the Stop Grant state by stopping the CLK input.

  • Page 183: Stop Clock Snoop State (Cache Invalidations)

    ® When the Write-Back Enhanced Intel Quark SoC X1000 Core is in either Standard or Enhanced Bus mode, and a FLUSH# event occurs during Auto HALT Power Down state, the processor transitions to the Auto HALT Power Down Flush state. If the on-chip...

  • Page 184: Bus Operation

    ® The Intel Quark SoC X1000 Core address signals are split into two components. High- order address bits are provided by the address lines, A[31:2]. The byte enables, BE[3:0]#, form the low-order address and provide linear selects for the four bytes of the 32-bit address bus.

  • Page 185: Memory And I/O Space Organization

    ® The Intel Quark SoC X1000 Core includes bus control pins, BS16# and BS8#, which allow direct connection to 16- and 8-bit memories and I/O devices. Cycles of 32-, 16- and 8-bits may occur in any sequence, since the BS8# and BS16# signals are sampled during each bus cycle.

  • Page 186: Dynamic Data Bus Sizing

    The simplest example of this function is a 32-bit aligned, BS16# read. When ® the Intel Quark SoC X1000 Core reads the two high order bytes, they must be driven ® on the data bus pins D[31:16]. The Intel Quark SoC X1000 Core expects the two low order bytes on D[15:0].

  • Page 187: Interfacing With 8-, 16-, And 32-Bit Memories

    Other pins in the data bus are driven but they contain no valid ® data. The Intel Quark SoC X1000 Core does not duplicate write data onto parts of the data bus for which the corresponding byte enable is deasserted. 10.1.3 Interfacing with 8-, 16-, and 32-Bit Memories ®...

  • Page 188: Intel ® Quark Soc X1000 Core With 32-Bit Memory

    Figure 80 shows the Intel Quark SoC X1000 Core address bus interface to 32-, 16- and 8-bit memories. To address 16-bit memories the byte enables must be decoded to produce A1, BHE# and BLE# (A0). For 8-bit wide memories the byte enables must be decoded to produce A0 and A1.

  • Page 189: Generating A1, Bhe# And Ble# For Addressing 16-Bit Devices

    ® Bus Operation—Intel Quark Core Table 64. Generating A1, BHE# and BLE# for Addressing 16-Bit Devices ® Intel Quark SoC X1000 Core 8-, 16-Bit Bus Signals Comments BE3# BE2# BE1# BE0# BHE# BLE# (A0) 1† 1† 1† 1† x–no asserted bytes 1†...

  • Page 190: Logic To Generate A1, Bhe# And Ble# For 16-Bit Buses

    ® Figure 82 shows a Intel Quark SoC X1000 Core data bus interface to 16- and 8-bit wide memories. External byte swapping logic is needed on the data lines so that data is ® supplied to and received from the Intel...

  • Page 191: Dynamic Bus Sizing During Cache Line Files

    Dynamic Bus Sizing during Cache Line Files ® BS8# and BS16# can be driven during cache line fills. The Intel Quark SoC X1000 Core generates enough 8- or 16-bit cycles to fill the cache line. This can be up to sixteen 8-bit cycles.

  • Page 192: Operand Alignment

    BS16# or BS8#, forcing extra cycles, low-order bytes or ® words are transferred first (opposite to the example above). When the Intel Quark SoC X1000 Core requests a 4-byte read and the external system asserts BS16#, the lower two bytes are read first followed by the upper two bytes.

  • Page 193: Bus Arbitration Logic

    DMA device. Once the DMA device completes its bus activity cycles, it negates the HOLD signal to relinquish the bus and return control to the processor. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 194: Single Intel Quark Core With Dma

    ® rotating scheme. The arbitration logic then passes information to the Intel Quark SoC X1000 Core, which ultimately releases the bus. The arbitration logic receives bus control status information via the HOLD and HLDA signals and relays it to the requesting devices.

  • Page 195: Single Intel Quark Core With Multiple Secondary Masters

    It is important that an arbitration scheme be selected to best fit the needs of each system's implementation. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 196: Bus Functional Description

    ® The Intel Quark SoC X1000 Core supports a wide variety of bus transfers to meet the needs of high performance systems. Bus transfers can be single cycle or multiple cycle, burst or non-burst, cacheable or non-cacheable, 8-, 16- or 32-bit, and pseudo-locked.

  • Page 197: Inserting Wait States

    ® The Intel Quark SoC X1000 Core samples RDY# at the end of the second clock. The cycle is complete if RDY# is asserted (LOW) when sampled. Note that RDY# is ignored at the end of the first clock of the bus cycle.

  • Page 198: Multiple And Burst Cycle Bus Transfers

    ® The Intel Quark SoC X1000 Core is capable of bursting a maximum of 32 bits during a write. Burst writes can only occur if BS8# or BS16# is asserted. For example, the ®...

  • Page 199: Terminating Multiple And Burst Cycle Transfers

    ® The Intel Quark SoC X1000 Core deasserts BLAST# for all but the last cycle in a multiple cycle transfer. BLAST# is deasserted in the first cycle to inform the external system that the transfer could take additional cycles. BLAST# is asserted in the last cycle of the transfer to indicate that the next time BRDY# or RDY# is asserted the transfer is complete.

  • Page 200: Non-Cacheable, Non-Burst, Multiple Cycle Transfers

    Each cycle in the transfer begins when ADS# is asserted and the cycle is complete when the external system asserts RDY#. ® The Intel Quark SoC X1000 Core indicates the last cycle of the transfer by asserting BLAST#. The next RDY# asserted by the external system terminates the transfer. 10.3.2.4 Non-Cacheable Burst Cycles The external system converts a multiple cycle request into a burst cycle by asserting BRDY# rather than RDY# in the first cycle of the transfer.

  • Page 201: Cacheable Cycles

    BRDY# during the first cycle of the transfer on the external bus. Once KEN# is asserted ® and the remaining three requirements described below are met, the Intel Quark SoC X1000 Core fetches an entire cache line regardless of the state of KEN#. KEN# must be asserted in the last cycle of the transfer for the data to be written into the internal ®...

  • Page 202: Byte Enables During A Cache Line Fill

    The cycle becomes a cache fill when the ® Intel Quark SoC X1000 Core samples KEN# asserted at the end of the first clock. The ® Intel Quark SoC X1000 Core deasserts BLAST# in the second clock in response to KEN#.

  • Page 203: Burst Cacheable Cycles

    ® The external system informs the Intel Quark SoC X1000 Core that it will burst the line in by asserting BRDY# at the end of the first cycle in the transfer. Note that during a burst cycle, ADS# is only driven with the first address.

  • Page 204: Effect Of Changing Ken# During A Cache Line Fill

    Figure 92. Note that the timing ® of BLAST# follows that of KEN# by one clock. The Intel Quark SoC X1000 Core samples KEN# every clock and uses the value returned in the clock before BRDY# or RDY# to determine if a bus cycle would be a cache line fill. Similarly, it uses the value of KEN# in the last cycle before early RDY# to load the line just retrieved from memory into the cache.

  • Page 205: Burst Mode Details

    10.3.4.1 Adding Wait States to Burst Cycles ® Burst cycles need not return data on every clock. The Intel Quark SoC X1000 Core strobes data into the chip only when either RDY# or BRDY# is asserted. Deasserting BRDY# and RDY# adds a wait state to the transfer. A burst cycle where two clocks are...

  • Page 206: Burst And Cache Line Fill Order

    ® The Intel Quark SoC X1000 Core presents each request for data in an order determined by the first address in the transfer. For example, if the first address was 104 the next three addresses in the burst will be 100, 10C and 108. An example of...

  • Page 207: Interrupted Burst Cycles

    64-bit read, or ® perform a pre-fetch. If either BS8# or BS16# is asserted, the Intel Quark SoC X1000 Core completes the transfer of the current 32-bit word before progressing to the next 32-bit word.

  • Page 208: Interrupted Burst Cycle

    96. The cycle had been converted to a cache fill in the first part of the ® transfer and the Intel Quark SoC X1000 Core expects the cache fill to be completed. Note that the first half and second half of the transfer in Figure 95 are both two-cycle burst transfers.

  • Page 209: 8- And 16-Bit Cycles

    ® The Intel Quark SoC X1000 Core supports both 16- and 8-bit external buses through the BS16# and BS8# inputs. BS16# and BS8# allow the external system to specify, on a cycle-by-cycle basis, whether the addressed component can supply 8, 16 or 32 bits.

  • Page 210: Bit Bus Size Cycle

    For example, a single non-cacheable read could be transferred by the Intel Quark SoC X1000 Core as four 8-bit burst data cycles. Similarly, a single 32-bit write could be written as four 8-bit burst data cycles. An example of a burst write is shown in Figure 98.

  • Page 211: Locked Cycles

    Locked cycles are implemented in hardware with the LOCK# pin. When LOCK# is ® asserted, the Intel Quark SoC X1000 Core is performing a read-modify-write operation and the external bus should not be relinquished until the cycle is complete. Multiple reads or writes can be locked. A locked cycle is shown in Figure 99.

  • Page 212: Pseudo-Locked Cycles

    ® For the Intel Quark SoC X1000 Core, examples include 64-bit description loads and cache line fills. Pseudo-locked transfers are indicated by the PLOCK# pin. The memory operands must be aligned for correct operation of a pseudo-locked cycle.

  • Page 213: Floating-Point Read And Write Cycles

    When the ® Intel Quark SoC X1000 Core finds a write to a section of external memory contained ® in its internal cache, the Intel Quark SoC X1000 Core's internal copy is invalidated.

  • Page 214: Fast Internal Cache Invalidation Cycle

    † † BREQ † To Processor 242202-091 Figure 102. Typical Internal Cache Invalidation Cycle ADS# † ADDR AHOLD EADS# RDY# † DATA BREQ † To Processor 242202-092 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 215: Rate Of Invalidate Cycles

    ® Quark SoC X1000 Core is retrieving data from the second-level cache. The Intel Quark SoC X1000 Core must invalidate a line in its internal cache if the external device ® is writing to a main memory address that is also contained in the Intel Quark SoC X1000 Core cache.

  • Page 216: System With Second-Level Cache

    Memory ® If the system asserts EADS# before the first data in the line fill is returned to the Intel Quark SoC X1000 Core, the system must return data consistent with the new data in the external memory upon resumption of the line fill after the invalidation cycle. This is illustrated by the asserted EADS# signal labeled “1”...

  • Page 217: Bus Hold

    ® complete. An example of a HOLD/HLDA transaction is shown in Figure 105. The Intel Quark SoC X1000 Core can respond to HOLD by floating its bus and asserting HLDA while RESET is asserted. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual...

  • Page 218: Hold/Hlda Cycles

    HOLD could be asserted simultaneously or after BOFF# and still be acknowledged. The pins floated during bus hold are: BE[3:0]#, PCD, PWT, W/R#, D/C#, M/O#, LOCK#, PLOCK#, ADS#, BLAST#, D[31:0], A[31:2], and DP[3:0]. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 219: 10Interrupt Acknowledge

    Interrupt Acknowledge ® The Intel Quark SoC X1000 Core generates interrupt acknowledge cycles in response to maskable interrupt requests that are generated on the interrupt request input (INTR) pin. Interrupt acknowledge cycles have a unique cycle type generated on the cycle type pins.

  • Page 220: 11Special Bus Cycles

    ® The Intel Quark SoC X1000 Core halts as a result of executing a HALT instruction. A HALT indication cycle is performed to signal that the processor has entered into the HALT state. The HALT indication cycle is identified by the bus definition signals in special bus cycle state and by a byte address of 2.

  • Page 221: 2Shutdown Indication Cycle

    ® The Intel Quark SoC X1000 Core shuts down as a result of a protection fault while attempting to process a double fault. A shutdown indication cycle is performed to indicate that the processor has entered a shutdown state. The shutdown indication cycle is identified by the bus definition signals in special bus cycle state and a byte address of 0.

  • Page 222: 12Bus Cycle Restart

    Quark SoC X1000 Core to complete its current bus request. In this situation, ® the Intel Quark SoC X1000 Core must restart its bus cycle after the other bus master has completed its bus transaction. A bus cycle may be restarted if the external system asserts the backoff (BOFF#) input.

  • Page 223: Restarted Write Cycle

    X1000 Core to ignore data returned for that cycle only. Data from previous cycles is still ® valid. For example, if BOFF# is asserted on the third BRDY# of a burst, the Intel Quark SoC X1000 Core assumes the data returned with the first and second BRDY# is correct and restarts the burst beginning with the third item.

  • Page 224: 13Bus States

    First clock cycle of a restarted bus cycle. Valid address and status are driven and ADS# is asserted. Second and subsequent clock cycles of an aborted bus cycle. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 225: Quark Soc X1000 Core

    Two pins, floating-point error (FERR#, an output) and ignore numeric error (IGNNE#, an input) are provided to direct the actions of hardware if user-defined error reporting ® is used. The Intel Quark SoC X1000 Core asserts the FERR# output to indicate that a floating-point error has occurred. ® ®...

  • Page 226: Quark Soc X1000 Core Floating-Point Error Handling In

    In systems with user-defined error reporting, the FERR# pin is connected to the interrupt controller. When an unmasked floating-point error occurs, an interrupt is ® raised. If IGNNE# is high at the time of this interrupt, the Intel Quark SoC X1000 Core freezes (disallowing execution of a subsequent floating-point instruction) until the interrupt handler is invoked.

  • Page 227: Burst Cycles

    When CACHE# is asserted on a read cycle, the processor follows with BLAST# high when KEN# is asserted. However, the converse is not true. The Write-Back Enhanced ® Intel Quark SoC X1000 Core may elect to read burst data that are identified as non- ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual...

  • Page 228: Burst Cycle Signal Protocol

    ® drive INV high to invalidate a particular cache line. The Write-Back Enhanced Intel Quark SoC X1000 Core does not have an output pin to indicate a snoop hit to an S- ® state line or an E-state line. However, the Write-Back Enhanced Intel Quark SoC ®...

  • Page 229: Snoop Collision With A Current Cache Line Operation

    Standard Bus mode. In Enhanced Bus mode, the Write-Back ® Enhanced Intel Quark SoC X1000 Core can accept EADS# every other clock period or until a snoop hits an M-state line. ® The Write-Back Enhanced Intel Quark SoC X1000 Core does not accept any further snoop cycles inputs until the previous snoop write-back operation is completed.

  • Page 230: Snoop Under Ahold

    Snooping under AHOLD begins by asserting AHOLD to force the Write-Back Enhanced ® Intel Quark SoC X1000 Core to float the address bus, as shown in Figure 113. The ADS# for the write-back cycle is guaranteed to occur no sooner than the second clock following the assertion of HITM# (i.e., there is a dead clock between the assertion of...

  • Page 231: Snoop Cycle Invalidating A Modified Line

    The assertion of AHOLD during a line fill is allowed on the Write-Back Enhanced Intel Quark SoC X1000 Core. In this case, when a snoop cycle is overlaid by an on-going line-fill cycle, the chipset must generate the burst addresses internally for the line fill to complete, because the address bus has the valid snoop address.

  • Page 232: Snoop Cycle Overlaying A Line-Fill Cycle

    ® Intel Quark SoC X1000 Core floats the address bus (not the Byte Enables). Hence, the memory controller must determine burst addresses in this period. The chipset must comprehend the special ordering required by all burst sequences of the Write-Back ®...

  • Page 233: Snoop Cycle Overlaying A Non-Burst Cycle

    1. The processor always snoops the line being filled. 2. In all cases, the processor uses the operand that triggered the line fill. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 234: Snoop During Replacement Write-Back

    In this case, the replacement write-back is converted to the snoop write-back, and HITM# is asserted and de-asserted without a specific ADS# to initiate the write- back cycle. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 235: Snoop Under Boff

    ® Table 67 Table 71) of the Write-Back Enhanced Intel Quark SoC X1000 Core are floated in the clock period following the assertion of BOFF#. If the system snoop hits a modified line using BOFF#, the snoop write-back cycle is reordered ahead of the current cycle.

  • Page 236: Snoop Under Boff# During A Cache Line-Fill Cycle

    ® Back Enhanced Intel Quark SoC X1000 Core accepts only up to the x4h doubleword, and the line fill resumes with the x0h doubleword. ADS# initiates the resumption of the line-fill operation in clock period 15. HITM# is de-asserted in the clock period following the clock period in which the last RDY# or BRDY# of the write-back cycle is asserted.

  • Page 237: Snoop Under Hold

    ® cycles, the Write-Back Enhanced Intel Quark SoC X1000 Core does not assert HLDA until the entire current cycle is completed. If the system snoop hits a modified line under HLDA during a non-cacheable, non-burstable code prefetch, the snoop write- back cycle is reordered ahead of the fractured cycle.

  • Page 238: Snoop Under Hold During Line Fill

    ® clock five, the Write-Back Enhanced Intel Quark SoC X1000 Core asserts HLDA and the system begins snooping by driving EADS# and INV in the following clock period. The assertion of HITM# in clock nine indicates that the snoop cycle has hit a modified line and the cache line is written back to memory.

  • Page 239: Snoop Under Hold During Replacement Write-Back

    10.4.4 Locked Cycles ® In both Standard and Enhanced Bus modes, the Write-Back Enhanced Intel Quark SoC X1000 Core architecture supports atomic memory access. A programmer can modify the contents of a memory variable and be assured that the variable is not accessed by another bus master between the read of the variable and the update of that variable.
  • Page 240 KEN# is asserted. If there are back-to-back locked cycles, the ® Write-Back Enhanced Intel Quark SoC X1000 Core does not insert a dead clock between these two cycles. HOLD is recognized if there are two back-to-back locked cycles, and LOCK# floats when HLDA is asserted.

  • Page 241: Snoop/Lock Collision

    ® operation. Figure 123 shows the flush operation of the Write-Back Enhanced Intel Quark SoC X1000 Core when configured in the Enhanced Bus mode. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual...

  • Page 242: Pseudo Locked Cycles

    AHOLD can fracture a 64-bit transfer if it is a non-burst cycle. If the 64-bit cycle is burst, as shown in Figure 124, the entire transfer goes to completion and only then does the snoop write-back cycle start. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 243: Snoop Under Hold During Pseudo-Locked Cycles

    Figure 125, HOLD does not fracture the 64-bit burst transfer. The Write- ® Back Enhanced Intel Quark SoC X1000 Core does not issue HLDA until clock four. ® After the 64-bit transfer is completed, the Write-Back Enhanced Intel Quark SoC X1000 Core writes back the modified line to memory (if snoop hits a modified line).

  • Page 244: Snoop Under Boff# Overlaying A Pseudo-Locked Cycle

    64-bit read cycle in clock four. If there is a snoop hit under BOFF#, the snoop write-back operation begins after BOFF# is deasserted. The 64-bit write cycle resumes after the snoop write-back operation completes. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 245: Snoop Under Boff# Overlaying A Pseudo-Locked Cycle

    Figure 126. Snoop under BOFF# Overlaying a Pseudo-Locked Cycle AHOLD EADS# HITM# † Write Back Cycle A31–A4 A3–A2 ADS# BLAST# CACHE# PLOCK# W/R# BRDY# † To Processor 242202-163 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 246: Debugging Support

    INT3 breakpoint opcode. ® The Intel Quark SoC X1000 Core contains six Debug Registers, providing the ability to specify up to four distinct breakpoint addresses, breakpoint control options, and read breakpoint status. Initially after reset, breakpoints are in the disabled state. Therefore, no breakpoints occur unless the debug registers are programmed.

  • Page 247: Linear Address Breakpoint Registers (Dr[3:0])

    72. The breakpoint addresses specified are 32-bit linear ® addresses. Intel Quark SoC X1000 Core hardware continuously compares the linear breakpoint addresses in DR[3:0] with the linear addresses generated by executing software (a linear address is the result of computing the effective address and adding the 32-bit segment base address).

  • Page 248: Leni Encoding

    11 are used to set up write-only or read/write data breakpoints. Table 74. RW Encoding RW Encoding Usage Causing Breakpoint Instruction execution only Data writes only Undefined–do not use this encoding Data reads and writes only ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 249 ® The Intel Quark SoC X1000 Core GE bit is unaffected during a task switch. The GE bit supports exact data breakpoint match that remains enabled during all tasks executing in the system. Note that instruction execution breakpoints are always reported exactly.

  • Page 250: Debug Status Register (Dr6)

    Note that the breakpoints must be re-enabled under software control. ® All Intel Quark SoC X1000 Core Gi bits are unaffected during a task switch. The Gi bits support breakpoints that are active in all tasks executing in the system. 11.3.3...

  • Page 251: Use Of Resume Flag (Rf) In Flag Register

    ® occurs on a task having a Intel Quark SoC X1000 Core TSS with the T bit set. Note the task switch into the new task occurs normally, but before the first instruction of the task is executed, the exception 1 handler is invoked. With respect to the task switch operation, the operation is considered to be a trap.

  • Page 252: Instruction Set Summary

    ® All Intel Quark SoC X1000 Core instructions operate on either 0, 1, 2 or 3 operands; where an operand resides in a register, in the instruction itself, or in memory. Most zero-operand instructions (e.g., CLI, STI) take only one byte. One-operand instructions generally are two bytes long.

  • Page 253: Floating-Point Instructions

    ® themselves. Table 75 is a complete list of all fields appearing in the Intel Quark SoC X1000 Core instruction set. Following Table 75 are detailed tables for each field.

  • Page 254: 32-Bit Extensions Of The Instruction Set

    32-Bit Extensions of the Instruction Set ® With the Intel Quark SoC X1000 Core, the instruction set is extended in two orthogonal directions: 32-bit forms of all 16-bit instructions support the 32-bit data types and 32-bit addressing modes are available for all instructions referencing memory.

  • Page 255: Encoding Of Integer Instruction Fields

    Encoding of reg Field when the (w) Field is Not Present in Instruction Register Selected during 16-Bit Register Selected during 32-Bit reg Field Data Operations Data Operations ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 256: Encoding Of The Segment Register (Sreg) Field

    The sreg field in certain instructions is a 2-bit field allowing one of the four segment registers to be specified. The sreg field in other instructions is a 3-bit field, allowing the ® Intel Quark SoC X1000 Core FS and GS segment registers to be specified. Table 79. 2-Bit sreg2 Field 2-bit sreg2 Field Segment Register Selected ®...

  • Page 257: Encoding Of Address Mode

    16-bit addressing mode specifier. When 32-bit addressing is used, the “mod r/m” byte is interpreted as a 32-bit addressing mode specifier. The following tables define encodings of all 16-bit and 32-bit addressing modes. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 258: Encoding Of 16-Bit Address Mode With "Mod R/M" Byte

    11 001 11 001 11 010 11 010 11 011 11 011 11 100 11 100 11 101 11 101 11 110 11 110 11 111 11 111 ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 259: Encoding Of 32-Bit Address Mode With "Mod R/M" Byte (No "S-I-B" Byte Present)

    11 001 11 001 11 010 11 010 11 011 11 011 11 100 11 100 11 101 11 101 11 110 11 110 11 111 11 111 ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 260: Encoding Of Operation Direction (D) Field

    Register/Memory ← Register “reg” Field Indicates Source Operand; “mod r/m” or “mod ss index base” Indicates Destination Operand Register ← Register/Memory “reg” Field Indicates Destination Operand; “mod r/m” or “mod ss index base” Indicates Source Operand ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 261: Encoding Of Sign-Extend (S) Field

    Not Less or Equal/Greater Than 1111 12.2.3.8 Encoding of Control or Debug or Test Register (eee) Field This field is used for loading and storing the Control, Debug and Test registers. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 262: Encoding Of Floating-Point Instruction Fields

    The s-i-b (Scale Index Base) byte and disp (displacement) are optionally present in instructions that have mod and r/m fields. Their presence depends on the values of mod and r/m, as for integer instructions. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 263: Intel ® Quark Soc X1000 Core Instructions

    111 = Eighth stack element ® 12.2.5 Intel Quark SoC X1000 Core Instructions ® The instructions below were added to the Intel Quark SoC X1000 Core (in microcode and in hardware for RDTSC). CMPXCHG8B CoMPare and eXCHanGe 8 Bytes RDMSR...

  • Page 264: Rdmsr

    EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset.

  • Page 265: Clock Count Summary

    Instruction Clock Count Assumptions ® The Intel Quark SoC X1000 Core instruction core clock count tables give clock counts assuming data and instruction accesses hit in the cache. The combined instruction and data cache hit rate is greater than 90%.
  • Page 266 9. No invalidate cycles. Add a delay of one bus clock for each invalidate cycle if the ® invalidate cycle contends for the internal cache/external bus when the Intel Quark SoC X1000 Core needs to use it. 10. Page translation hits in TLB. A TLB miss adds 13, 21 or 28 bus clocks + 1 possible core clock to the instruction depending on whether the Accessed and/or Dirty bit in neither, one, or both of the page entries must be set in memory.

  • Page 267: Clock Count Summary

    Memory with reg 1000 011w : mod reg r/m NOP = No Operation 1001 0000 Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 268 0011 110w : immediate data 1000 00sw : mod 111 r/m : immediate immediate with memory data Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 269 Multiplier-Byte 13/18 MN/MX,3 Word 13/26 MN/MX,3 Dword 13/42 MN/MX,3 Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 270 1111 011w : mod 11 1 r/m Divisor-Byte Word Dword CBW = Convert Byte to 1001 1000 Word Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 271 0000 1111 : 1011 000w : 11 reg2 reg1 memory, reg 0000 1111 : 1011 000w : mod reg r/m 7/10 Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 272 1111 1111 : 11 010 reg 7,23 Memory Indirect 1111 1111 : mod 010 reg Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 273 (d) words 77+4X 24+n P,11,9 to TSS 37+TS P,10,9 thru Task Gate 38+TS P,10,9, Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 274 MN/MX, 14 memory, reg 0000 1111 : 1011 1101 : mod reg r/m 7/104 MN/MX, 15 Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 275 1111 1001 CMC = Complement Carry 1111 0101 Flag CLD = Clear Direction Flag 1111 1100 Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 276 EAX = 0, >1 CLTS = Clear Task Switched 0000 1111 : 0000 0110 Flag Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 277 0000 1111 : 0000 0011 : 11 reg1 reg2 From memory 0000 1111 : 0000 0011 : mod reg r/m Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 278 Real Mode/Virtual Mode Protected Mode To same level To outer level To nested task TS+32 9,10 (EFLAGS.NT=1) Note: Table 92 for notes and abbreviations for items in this table. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 279: Fixed)

    Quark SoC X1000 Core/286 TSS to Intel Quark SoC X1000 Core TSS ® VM/Intel Quark SoC X1000 Core/286 TSS to 286 TSS Note: Table 92 for definitions and notes for items in this table. Table 91. Interrupt Clock Counts (Sheet 1 of 2)

  • Page 280: Notes And Abbreviations

    RV/P real and virtual mode/protected mode real mode protected mode T/NT taken/not taken H/NH hit/no hit The following notes refer to Table 89 through Table ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 281: I/O Instructions Clock Count Summary

    Two clock cache miss penalty in all cases. c = count in CX or ECX. Cache miss penalty in all modes: Add two clocks for every 16 bytes. Entire penalty on second operation. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 282 Two clock cache miss penalty in all cases. c = count in CX or ECX. Cache miss penalty in all modes: Add two clocks for every 16 bytes. Entire penalty on second operation. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 283: Floating-Point Clock Count Summary

    The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 284 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 285 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 286 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 287 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 288 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...
  • Page 289 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...
  • Page 290 The INT pin is polled several times while this function is executing to ensure short interrupt latency. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)). ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 291: Signal Descriptions

    Symbol Type Name and Function ® Clock provides the fundamental timing and the internal operating frequency for the Intel Quark Core. All external timing parameters are specified with respect to the rising edge of CLK. ADDRESS BUS The Address Lines A[31:2], together with the byte enables signals BE[3:0]#, define the physical area of A[31:4], memory or input/output space accessed.

  • Page 292: Intel ® Quark Soc X1000 Core Pin Descriptions

    Name and Function ® The Bus Lock pin indicates that the current bus cycle is locked. The Intel Quark Core does not allow a bus hold when LOCK# is asserted (but address holds are allowed). LOCK# goes active in the first clock of LOCK# the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle.
  • Page 293 CACHE CONTROL ® The Cache Enable pin is used to determine whether the current cycle is cacheable. When the Intel Quark Core generates a cycle that can be cached and KEN# is active one clock before RDY# or BRDY# during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Asserting KEN# one clock KEN# before RDY# during the last read in the cache line fill causes the line to be placed in the on-chip cache.
  • Page 294 BUS SIZE CONTROL ® The Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the Intel Quark Core to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle.
  • Page 295 ® Signal Descriptions—Intel Quark Core ® Table 95. Intel Quark SoC X1000 Core Pin Descriptions (Sheet 5 of 5) Symbol Type Name and Function ® WRITE-BACK ENHANCED Intel Quark Core SIGNAL PINS The CACHE# output indicates internal cacheability on read cycles and burst write-back on write cycles.

  • Page 296: Testability

    ® The Intel Quark SoC X1000 Core contains a cache fill buffer and a cache read buffer. For testability writes, data must be written to the cache fill buffer before it can be written to a location in the cache. Data must be read from a cache location into the cache read buffer before the processor can access the data.

  • Page 297: Cache Testability Write

    TR5 specifies the testability operation to be performed and the set and entry to be ® accessed. The set select field determines the set to be accessed. Note that the Intel Quark SoC X1000 Core has an 8-bit set select field and 256 sets.

  • Page 298: Cache Testability Read

    ® select. The Intel Quark SoC X1000 Core has an eight-bit select field. In response to the write to TR5, TR4 is loaded with the 21-bit tag field and the single valid bit from the cache entry read. TR4 is also loaded with the three LRU bits and four valid bits corresponding to the cache set that was accessed.

  • Page 299: Flush Cache

    ® Intel Quark SoC X1000 Core ® When in Enhanced Bus (Write-Back) mode, the Write-Back Enhanced Intel Quark SoC X1000 Core cache testing is a superset of the Standard Bus (Write-Through) mode. The additional cache testing features are summarized below.

  • Page 300: Translation Lookaside Buffer (Tlb) Testing

    B.2.1 Translation Lookaside Buffer Organization ® The Intel Quark SoC X1000 Core TLB is 4-way set associative and has space for 32 entries. The TLB is logically split into three blocks shown in Figure 132. The data block is physically split into four arrays, each with space for eight entries. An entry in the data block is 22 bits wide containing a 20-bit physical address and two bits for the page attributes.

  • Page 301: Tlb Test Registers Tr6 And Tr7

    The upper 17 bits of the linear address form the tag stored in the tag array. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 302: Tlb Test Registers

    Match TLB TAG Bit B if 1 Undefined Match any TLB TAG Bit B Table 99. TR6 Operation Bit Encoding TR6 Bit 0 TLB Operation to Be Performed TLB Write TLB Lookup ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 303: Data Test Register: Tr7

    TR7 bits 3-2 or the internal LRU bits as the replacement pointer on the TLB write operation. Note that the LRU bits in TR7 are not used in a write test. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 304: Tlb Lookup Test

    Intel Quark SoC X1000 Core JTAG ® The Intel Quark SoC X1000 Core provides additional testability features compatible with the IEEE Standard Test Access Port. B.3.1 Test Access Port (TAP) Controller The TAP controller is a synchronous, finite state machine. It controls the sequence of operations of the test logic.

  • Page 305: Test-Logic-Reset State

    If TMS is held high and a rising edge is applied to TCK, the controller moves to the Select-IR-Scan state. The instruction does not change in this state. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 306: Capture-Dr State

    Shift-DR state. The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 307: Update-Dr State

    The instruction does not change in this state. B.3.1.14 Pause-IR State The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 308: Exit2-Ir State

    The TAP controller is automatically initialized when a device is powered up. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for five TCK periods. ® Intel Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US...

  • Page 309: C Feature Determination

    When the value of Limit CPUID Maxval (bit 22 of IA32_MISC_ENABLE) is set to 1, all basic leaves above 3 should be invisible. In this case, leaf 7 returns all zeros. ® Intel Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US...

  • Page 310: Intel ® Quark Soc X1000 Cpuid

    ® The Intel Quark SoC X1000 Core implements the CPUID instruction to make information available to the system software about the family, model, and stepping of the processor. Support of this instruction is indicated by the ability of system software to write and read the bit in position EFLAGS.21, referred to as the EFLAGS.ID bit.

  • Page 311: Intel ® Quark Soc X1000 Stepping

    ® Feature Determination—Intel Quark Core Refer to the Intel application note, Intel Processor Identification with the CPUID Instruction, for more details: http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid- instruction-note.html link ® Intel Quark SoC X1000 Stepping ® The Intel Quark SoC X1000 stepping is identified by both: •...

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