Trace Transitioning Layers And Crossing Plane Splits - Intel Quark SoC X1000 Design Manual

LAN Design Considerations and Guidelines—Intel
If the transition is from power-referenced layer to a ground-referenced layer or from
one voltage-power referenced layer to a different voltage-power referenced layer, then
stitching capacitors should be used within 40 mils of the transition.
If the transition is from one ground-referenced layer to another ground-referenced
layer or is from a power-referenced layer to the same net power-referenced layer, then
connecting vias should be used within 40 mils of the transition.
Figure 97.

Trace Transitioning Layers and Crossing Plane Splits

Transitioning Reference Layers
Top Layer
Crossing Plane Splits-Use Stitching Capacitors
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Stitching capacitor
<40 mils
Lower Layer
via
+3.3 Vdc
GND plane
plane
10 pF
Do not
trace under
3.3 Vdc plane
edge of a
5.0 Vdc plane
Distance from stitching capacitor
Board
Layers
Connection Vias
GND to GND
run
Connection Vias
plane
PWR to same PWR
Trace
10 pF
{ to any via is <40 mils
copper
3.3 V power
GND
copper
<40 mils
copper
GND
copper
power
copper
GND
copper
<40 mils
copper
PWR 3.3 Vdc
copper
GND
copper
PWR 3.3 Vdc
copper
®
Intel Quark™ SoC X1000
PDG
159