Critical Low Speed Signals Design Guidelines; Critical Low Speed Signals General Introduction; Description; Critical Low Speed Signal Descriptions - Intel Quark SoC X1000 Design Manual

Critical Low Speed Signals Design Guidelines—Intel
16.0

Critical Low Speed Signals Design Guidelines

16.1

Critical Low Speed Signals General Introduction

16.1.1

Description

Critical Low Speed Signals are identified as critical input signals from the Intel
Quark™ SoC X1000 that are low frequency but have huge impact to system
functionality or stability. Glitches on these signals may cause system to behave in
unpredicted manners or cause unpredicted system shutdown or reset. Although these
are low speed signals in nature, glitches may be induced or coupled from nearby high
speed signals. Therefore it is important to keep these signals clean from any potential
sources of glitches on the platform.
16.2

Critical Low Speed Signal Descriptions

16.2.1

Signals Group

Signals listed in
Quark™ SoC X1000 that must be guaranteed glitch free all the time.
Table 53.

Critical Signals

Group
RTC
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
June 2014
Order Number: 330258-002US
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Quark™ SoC X1000
Table 53 below are identified as critical input signals from the Intel
Signal Name
RTC Reset: When asserted, this signal resets register bits in the
RTCRST_B
RTC well.
Power OK: When asserted, PWROK is an indication to the SoC
S5_PG that all of its S5 power rails have been stable for 10 ms. S5_PG
can be driven asynchronously.
Power OK: When asserted, indicates that power to the S3 power
S3_PG
rails are stable.
Power OK: When asserted, indicates that power to the S0 1P0v
S0_1P0_PG
power rail is stable.
Power OK: When asserted, indicates that power to the S0 1P5v
OSYSPWRGOOD
power rail is stable.
Power Button: The Power Button will indicate to the system a
request to go to S0. If the system is already in a sleep state S3,
this signal will cause a wake event. If PWRBTN# is pressed for
PWR_BTN
more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Forced shutdown is only
active in the S0 state.
PCI Express* Wake Event: Sideband wake signal on PCI
WAKE_B
Express asserted by components requesting wake up.
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Description
®
Intel Quark™ SoC X1000
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PDG
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