Intel Quark SoC X1000 Design Manual page 4

4.1.3 PCI Express* Lane Polarity Inversion .........................................................41
4.1.4 PCI Express* Port Lane Reversal...............................................................42
4.1.5 PCH PCIe* Disabling and Termination Guidelines.........................................42
4.1.6 Length Matching Guidelines......................................................................42
4.1.7 Impedance Compensation and Voltage Reference........................................42
4.1.8 Reference Documents..............................................................................43
4.2 PCIe* Signal Descriptions ...................................................................................43
4.2.1 Signal Groups ........................................................................................43
4.3 PCIe* Topology Guidelines ..................................................................................43
4.3.1 Expansion Card Connector Topology ..........................................................44
5.0 Universal Serial Bus 2.0 Design Guidelines...............................................................47
5.1 USB 2.0 General Introduction ..............................................................................47
5.1.1 Description ............................................................................................47
5.1.2 Compliance Documents ...........................................................................47
5.2 USB 2.0 Signal Descriptions ................................................................................48
5.2.1 Signal Groups ........................................................................................48
5.2.2 Overcurrent Protection ............................................................................48
5.3 USB 2.0 Topology Guidelines ...............................................................................49
5.3.1 External Topologies.................................................................................49
5.3.2 USB Connector Recommendations.............................................................52
5.3.2.1
5.3.3 Daughter Card .......................................................................................53
5.3.3.1
5.4 USB 2.0 Stackup Guidelines ................................................................................53
5.4.1 Stackup and Layer Utilization Guidelines ....................................................53
5.5 USB 2.0 Configuration, Connectivity, Block Diagram ...............................................53
5.5.1 Port Power Delivery.................................................................................54
5.6 USB 2.0 Length Matching Guidelines.....................................................................54
5.6.1 Length Matching and Length Formulas .......................................................54
5.7 USB 2.0 Additional Guidelines..............................................................................54
5.7.1 EMI and ESD Protection ...........................................................................54
5.8 USB 2.0 Disabling and Termination Guidelines .......................................................54
6.0 I2C* Interface Design Guidelines.............................................................................55
6.1 I2C* General Introduction...................................................................................55
6.1.1 Description ............................................................................................55
6.1.2 Reference Specifications ..........................................................................55
6.2 I2C* Signal Descriptions .....................................................................................55
6.2.1 Signal Groups ........................................................................................55
6.3 I2C* Topology Guidelines....................................................................................56
6.3.1 General Design Considerations .................................................................56
6.3.2 Detailed Routing Requirements.................................................................56
6.4 I2C* Connectivity ..............................................................................................57
6.5 I2C* Additional Guidelines ..................................................................................58
6.6 Terminating Unused I
7.0 SDIO Interface Design Guidelines ............................................................................59
7.1 SDIO General Introduction ..................................................................................59
7.1.1 Description ............................................................................................59
7.2 SDIO Signal Descriptions ....................................................................................59
7.2.1 Signal Groups ........................................................................................59
7.3 SDIO Topology Guidelines...................................................................................60
7.4 Terminating Unused SDIO Signals ........................................................................60
8.0 UART Interface Design Guidelines............................................................................63
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Intel Quark™ SoC X1000
PDG
4
External Connector Recommendations..........................................52
Daughter Card Design Guidelines ................................................53
2
C Signals...........................................................................58
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Intel Quark™ SoC X1000-Contents
Order Number: 330258-002US
June 2014