Intel Quark SoC X1000 Design Manual page 32

Table 8. DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 2 of 2)
Parameter
Trace Spacing (S2):
Between adjacent data
bytes' signals of a
channel
Trace Spacing (S3):
Between DQS and
DQS# pair
Trace Spacing (S4):
Between DQS/DSQ#
and DQ/DM
Trace Spacing (S5):
Between DQ/DM/DQS
group and other DDR
group's signals
Trace Spacing (S6):
Between DQ/DM/DQS
group and other non-
DDR signals - excluding
power pins
DQ/DQS Trace Segment
Length
DQ/DQS Total trace
length
Length matching
between DQ/DM and
DQ/DM within a Byte
group (including pkg.
length)
Length matching
between DQ/DM and
DQS/DQS# of a byte
(including pkg. length)
Length matching
between Clock and
DQS/DQS# (including
pkg. length)
Length matching
between DQS and DQS#
(including pkg. length)
Number of vias
SoC Buffer Settings:
SoC Read ODT:
DRAM BUffer Settings:
DRAM Runtime:
DRAM Ritter:
®
Intel Quark™ SoC X1000
PDG
32
®
Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines
Routing Guideline / Setting
min = 10.0 mils min = 20 mils
4.0 mils
min = 4.0 mils min = 13 mils
min = 4.0 mils min = 13 mils
min = 10.0 mils min = 25 mils
min = 500 mils
max = 300 mils
max = 2000 mils
TL1 + TL2 + TL3 = 2600 mils (max)
Note: All DM/DQ signals length for a given
Byte Group must fall within 10 mils window.
DQ = (DQ/DQSB ± 5 mils)
DQS = (CLK/CLKB - 1.75") ± 0.75"
dynamic ODT not used
min = 10.0 mils
4.7 mils
min = 4.0 mils
min = 4.0 mils
min = 10.0 mils
max = 300 mils
± 5 mils
± 5 mils
max = 2 via
RON: 32 Ω
SR: 4V/ns
180 Ω
RON: 34 Ω
120 Ω
Order Number: 330258-002US
4.0 mils
June 2014