Usb 2.0 External Routing Guidelines Microusb - Intel Quark SoC X1000 Design Manual

Table 22.

USB 2.0 External Routing Guidelines MicroUSB

PCB Routing Layer(s) optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Differential)
Trace Width (w)
Trace Spacing (S1): Between P and N of
clock pair
Trace Spacing (S2): Between USB2
different pairs
Trace Spacing (S3): Between USB2 pairs
and other signals
Trace Segment Length
Note: Recommend a cable length of 9" or less for connectivity from a microUSB to panel based standard
USB connector.
Length Matching Rules
Length Matching between P and N within a diff. pair
General
Number of vias
Routing Symmetry
Layer Assignment
Reference plane
MCH Settings
®
Intel Quark™ SoC X1000
PDG
50
®
Intel Quark™ SoC X1000—Universal Serial Bus 2.0 Design Guidelines
Breakout 1
4 Layer
L
A
MS
90 Ω +/-
10%
4.0 mil
4.0 mil
6.0 mil
6.0 mil
0.5" max
4 Layer 4 Layer
L L
B C
MS MS
90 Ω +/- 90 Ω +/-
10% 10%
4.0 mil 4.0 mil
6.0 mil 6.0 mil
15 mil 15 mil
25 mil 25 mil
0.1" - 2.0" 0.2" max
+/- 5 mil
max 3 vias
Symmetrical routing of P and N of a diff
pair including vias
See recommendations above
Ground Only
Gold_cie69_usb2_tx_drv_hspice_rev1p0_
ww28
vswing = 0.42
Preemp = 0.19054 (40mV)
Order Number: 330258-002US
4 Layer
L
E
MS
90 Ω +/-
10%
4.0 mil
6.0 mil
15 mil
25 mil
0.5" max
June 2014