Esd Ground-Fill; Ground-Fill Background; Mutual L And C (Lm, Cm) Coupling - Intel Quark SoC X1000 Design Manual

Electrostatic Discharge (ESD)—Intel
18.2.1

ESD Ground-Fill

Reducing sensitivity to Electrostatic Discharge (ESD) to ensure Intel products comply
with ESD standards can be a time and cost intensive effort. This section recommends
changes to the printed circuit board design that will reduce ESD sensitivity by
implementing a low impedance ESD current path to ground, thereby, reducing the
coupling to sensitive circuitry.
18.2.2

Ground-Fill Background

The premise of system ESD is that the discharge produces a surge through the chassis
that induces voltage and current fields within the system. The induced fields produce
negative effects to the board and components. The strength of the field coupling is
limited by the ESD spectral content, the chassis material thickness and skin depth, size
of coupled object, and proximity to the source. The coupling mechanism is a product of
mutual inductance and capacitance shown in
according to the dimensions of the victim as expressed in equations (1).
Figure 75.

Mutual L and C (Lm, Cm) Coupling

The induced voltage can be express as (1):
It is therefore expected that short and thin transmission lines couple very little energy
from the chassis discharge, while larger structures like a heatsink, packages, long and
thick power traces will couple the bulk of the energy. However, as signal noise margins
have shrunk over time, it does not take very much induced noise to disrupt these
signals. The area of the chassis that historically has high ESD coupling is the I/O area
due to the many penetrations in the chassis necessary to allow the I/O to connect to
peripherals. How well these I/O connections are RF bridged, directly impacts the
strength of the coupled noise. Along with good I/O shield ground connections, printed
circuit board grounding has been heavily depended on to dampen/reduce the coupled
energy.
It is the intention to use the naturally occurring coupling to dampen the ESD energy at
the most sensitive I/O area through the creation of an electrical large ground fill
structure. A metal ground shape will act as a low-pass filter which effectively lowers the
Q of coupled circuits. The thickness of the ground fill is required to be greater than the
calculated skin depth otherwise currents will form on both sides of the plane. The skin
depth can be calculated in the following expression:
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000

V jk sin

2
V 

2
1 k cos
1

Figure 75. The energy is high-pass filtered
 



 is the ¼ λ
sin
0
1

 
f

/( 2 )
0
®
Intel Quark™ SoC X1000
PDG
129