Sensitive Nets; Signal Integrity Analysis With Series Rc Filters - Intel Quark SoC X1000 Design Manual

Electrostatic Discharge (ESD)—Intel
Figure 80.

Signal Integrity Analysis With Series RC Filters

18.2.5

Sensitive Nets

Understanding the sensitivity of each signal nets to ESD noise may be very helpful for
designing and debugging a system for ESD. Certain nets on the platform may have
higher sensitivity to ESD noise and have severe impacts to the system. They need extra
care in circuit layout. The aforementioned ESD protection circuits may also be
populated for such nets to ensure the ESD robustness of the system. It is critical to
identify such sensitive nets among hundreds of nets on the platform and narrow down
the potential victims to ESD injections. This significantly reduces the required time and
cost to solve ESD-related issues.
A test approach to assess net sensitivities on Intel platforms has been developed. In
this approach, Transmission line pulser (TLP) is employed to generate a sharp and short
pulse to emulate ESD noise. Rising time and pulse width of this pulse are typically less
than 5 ns and 50 ns, respectively. It is injected into the system through a TLP probe
that directly touch the net under test with ohmic contact, as shown in
commonly-used ESD guns that have large unshielded tip and chassis, the TLP probe is
shielded to the very tip and has very limited coupling to proximity nets. This approach
focuses on one single net and eliminates the possibilities of stimulating proximity nets.
On the contrast, using ESD guns to investigate net sensitivity may be quite misleading.
Direct-zapping using ESD guns may stimulate proximity nets and make it difficult to
isolate the sensitivity from these proximity nets.
The tested sensitive nets are listed in
are upset are also included. This may be helpful for victim identifying during system
debugging.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Table 60. The typical symptoms when these nets
Intel
Figure 81. Unlike
®
Quark™ SoC X1000
PDG
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