Reference Specifications; Esd Protection; Iec 61000-4-2 Esd Waveform - Intel Quark SoC X1000 Design Manual

Figure 74.

IEC 61000-4-2 ESD Waveform

18.1.2

Reference Specifications

IEC 61000-4-2
18.2

ESD Protection

Selection criteria for discreet ESD protection devices must include consideration for the
electrical constraints of the interface needing protection. Many discreet semiconductor
ESD manufacturers now manufacturer devices for specific low- and high-speed
interfaces.
When considering an ESD protection device, it is recommended to select a device with
the highest rating against IEC 61000-4-2 air and contact discharge. Typically, the
device should be able to withstand a minimum air discharge of ±15 kV and a contact
discharge of ±8 kV. Clamping or holding voltage is another parameter that must be
selected based on the EOS (Electrical Over Stress) rating of the interface. The lower the
clamping voltage rating, the less residual energy will couple to the interface. As
signaling BW increases, capacitive loading becomes a serious concern when placing a
device on a high-speed interface. The maximum capacitive loading must be considered
as it relates to line-to-line and line-to-ground loading. Many devices are being designed
to work in the sub-pF range to handle the lower load requirements of high-speed
interfaces.
ESD device selection is summarized as:
1) Can withstand IEC ESD levels
2) Determine maximum clamping voltage before EOS
3) Determine maximum capacitive loading allowed
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Intel Quark™ SoC X1000
PDG
128
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Intel Quark™ SoC X1000—Electrostatic Discharge (ESD)
Title Location
http://www.iec.ch/
Order Number: 330258-002US
June 2014