Differential Routing Considerations; Stitching Via Usage And Placement; Single Ended Clock Routing Topology; Single Ended Clock Topology For Soc - Intel Quark SoC X1000 Design Manual

10.3.1.1

Differential Routing Considerations

When routing differential clocks, note the following recommendations:
• Ground referencing is preferred. However, differential clocks can be routed
referenced to other planes through the use of stitching capacitors to provide the
appropriate decoupling where the signal crosses planes.
• Do not split up the two halves of a differential clock pair between layers. Route to
all agents on the same physical routing layer referenced to ground.
— Typical routing assumes 1 layer transition within 500 mils of the SoC package
and a second layer transition within 500 mils of the destination ball.
— If a layer transition is required, both clock traces of the differential clock pair
must transition layers at the same length ±100 mils.
— If an additional layer transition is required, use simulations to ensure the skew
induced by the vias used to transition between routing layers is compensated in
the traces to other agents.
• Do not place vias between adjacent complementary clock traces and avoid
differential vias. Vias, placed in one signal of a differential-pair must be matched by
a via in the complement. Differential vias can be placed within length BO if needed
to shorten length BO.
No length matching is required between different source pairs.
10.3.1.2

Stitching Via Usage and Placement

Stitching vias must be used when signal traces change layers from top layer to bottom
or internal layer. In these cases reference GND layer associated with top signal layer
has to be connected with GND reference layer associated with bottom or internal signal
layer using GND stitching via. Placing GND stitching via according current guidelines
maintains optimal current return path and minimize crosstalk effect.
• Stitching vias should be placed with this spacing:
— 30-mils (0.762-mm) pitch between differential clock via and closest stitching
GND-via.
— Every differential clock via must have at least one GND stitching via with a
maximum spacing of 30 mils (0.762 mm).
• Placement of additional stitching vias, where possible, is recommended.
Motherboard GND stitching vias placement for differential clock signals.
10.3.2

Single Ended Clock Routing Topology

Figure 37.

Single Ended Clock Topology for SoC

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Quark™ SoC X1000—Platform Clocks Design Guidelines
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June 2014
Order Number: 330258-002US