Power-Well Isolation Control Signal Requirements; Platform_S5_Pwrok Generation; Platform_S5_Pwrok Generation; 10Platform_S3_Pwrok Generation - Intel Quark SoC X1000 Design Manual

Platform Reset Considerations—Intel
15.3.8

Power-well Isolation Control Signal Requirements

15.3.9

platform_s5_pwrok Generation

The platform_s5_pwrok signal is generated from the platform regulator V1P5 or
equivalent detection logic. The signal should be generated based on the v1p5 rail
achieving 90% of its nominal value
Figure 49.

platform_s5_pwrok generation

POWER BRICK
15.3.10 platform_S3_pwrok Generation
The platform_s3_pwrok signal is generated from the platform power switched S3 V1P5
or equivalent detection logic. The signal should be generated based on the S3 v1p5 rail
achieving 90% of its nominal value. The S3 v3p3 and v1p5 rails are enabled by SoC via
the v3p3_s3_en and v1p5_s3_en sequence.
15.3.11 platform_S0_1P0_pwrok Generation
The platform_s0_1p0_pwrok signal is generated from the platform regulator S0 V1P0
or equivalent detection logic. The signal should be generated based on the S0 v1p0 rail
achieving 90% of its nominal value. The v1p0 rail is enabled by SoC via the
v1p0_s0_en.
15.3.12 platform_S0_1P5_pwrok Generation
The platform_s0_1p5_pwrok signal is generated from the platform power switched S0
V1P5 or equivalent detection logic. The signal should be generated based on the S0
v1p5 rail achieving 90% of its nominal value. The S0 v3p3 and v1p5 rails are enabled
by SoC via the v3p3_s0_en and v1p5_s0_en sequence.
15.3.13 Glue Logic Device
Glue Logic Devices are available from various vendors to provide an ASIC component
that integrates miscellaneous platform logic into a single chip.
Contact your preferred vendor for available glue logic solution.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
1P5 VREG
en
RC Delay
3P3 VREG
en
Tied on
3P3_gd
VCC1P5_S5
platform_s5_pg
VCC3P3_S5
®
Intel Quark™ SoC X1000
PDG
103