Via Placement And Via Usage Optimization - Intel Quark SoC X1000 Design Manual

General Differential Signals Design Guidelines—Intel
Figure A-6. Differential-Pair Spacing Diagram
Figure A-7. Symmetrical and Non-Symmetrical Routing Example
A.4.2

Via Placement and Via Usage Optimization

• Vias impact the overall loss and jitter budget. Route signals with a minimal number
of vias.
• The via count can be reduced but not increased from the maximum interface via
requirements given in this document.
• Remove pads from unused internal layers to minimize excess via capacitance.
• The differential-pair via placement must be symmetrical. Vias on the differential-
pair should not only match in number but also in relative location.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
IPP Pitch
W PTPS DPS
Avoid: Non-symmetrical Routing
Preferred: Symmetrical Routing
®
Intel Quark™ SoC X1000
PDG
175