Programmable Clock Module Switch Position Chart; Four-Pole Sw Dip2 Settings; Eight-Pole Sw Dip1 Settings - Xilinx Virtex-5 FPGA ML550 User Manual
Networking interfaces platform
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Also See for Virtex-5 FPGA ML550:
- User manual (385 pages) ,
- User manual (28 pages) ,
- User manual (140 pages)
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Chapter 2: Getting Started
10. The GUI reflects the frequency set at Clock Module 2 and initially reports 400 MHz.
11. The clock frequency can be changed by clicking on the +100 MHz, +10 MHz,
Programmable Clock Module Switch Position Chart
Four-Pole SW DIP2 Settings
Eight-Pole SW DIP1 Settings
18
Select change to COM# where # is either 1, 2, 3, or 4.
More information resides in the file
C:\ML550 BERT REV1.x\DDR_8TO1_16CHAN_PICO_REV1.x\README.doc.
Also refer to the ML550 Networking Interfaces Board.ppt presentation on
the kit CD-ROM.
–100 MHz, and –10 MHz GUI buttons to the left of the Frequency display. More
detailed information is available in the CD file BERTGUI_README.doc.
Switch Position
1
Always
OFF
OFF
1
700 MHz
OFF
ON
690 MHz
ON
OFF
680 MHz
OFF
OFF
670 MHz
ON
ON
660 MHz
OFF
ON
650 MHz
ON
OFF
600 MHz
OFF
OFF
400 MHz
OFF
OFF
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2
3
4
OFF
OFF
Switch Position
2
3
4
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ML550 Networking Interfaces Platform
5
6
7
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
UG202 (v1.4) April 18, 2008
R
8
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
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