Feature Control Error Status Register; Video Mode Control And Status Registers For Format_7; Quadlet Offset Format_7 Mode_0; Quadlet Offset Format_7 Mode_1 - AVT Pike Technical Manual

Configuration of the camera
Offset Name
640h Feature_Control_Error_Status_HI
644h Feature_Control_Error_Status_LO
Offset
000h
004h
008h
00Ch
010h
014h

Feature control error status register

Table 119: Feature control error register
Video mode control and status registers for
Format_7

Quadlet offset Format_7 Mode_0

The quadlet offset to the base address for Format_7 Mode_0, which can be
read out at F0F002E0h (according to
on page 241) gives 003C2000h.
4 x 3C2000h = F08000h so that the base address for the latter
Format_7 control and status register
F0000000h + F08000h = F0F08000h.

Quadlet offset Format_7 Mode_1

The quadlet offset to the base address for Format_7 Mode_1, which can be
read out at F0F002E4h (according to
on page 241) gives 003C2400h.
4 x 003C2400h = F09000h so that the base address for the latter
Format_7 control and status register
F0000000h + F09000h = F0F09000h.

Format_7 control and status register (CSR)

Name
MAX_IMAGE_SIZE_INQ
UNIT_SIZE_INQ
IMAGE_POSITION
IMAGE_SIZE
COLOR_CODING_ID
COLOR_CODING_INQ
Table 120: Format_7 control and status register
Notes
Always 0
Always 0
Table 113: Frame rate inquiry register
on page 261) equals
Table 113: Frame rate inquiry register
on page 261) equals
Notes
According to IIDC V1.31
According to IIDC V1.31
According to IIDC V1.31
According to IIDC V1.31
See note
According to IIDC V1.31
PIKE Technical Manual V4.1.0
(Table 120:
(Table 120:
261