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AC SPECIFICATIONS
Relative Timings (80C186EA25 20 13 80L186EA13 8)
Symbol
RELATIVE TIMINGS
T
ALE Rising to ALE Falling
LHLL
T
Address Valid to ALE Falling
AVLL
T
Chip Selects Valid to ALE Falling
PLLL
T
Address Hold from ALE Falling
LLAX
T
ALE Falling to WR Falling
LLWL
T
ALE Falling to RD Falling
LLRL
T
RD Rising to ALE Rising
RHLH
T
WR Rising to ALE Rising
WHLH
T
Address Float to RD Falling
AFRL
T
RD Falling to RD Rising
RLRH
T
WR Falling to WR Rising
WLWH
T
RD Rising to Address Active
RHAV
T
Output Data Hold after WR Rising
WHDX
T
WR Rising to DEN Rising
WHDEX
T
WR Rising to Chip Select Rising
WHPH
T
RD Rising to Chip Select Rising
RHPH
T
CS Inactive to CS Active
PHPL
T
DEN Inactive to DT R Low
DXDL
T
ONCE (UCS LCS) Active to RESIN Rising
OVRH
T
ONCE (UCS LCS) to RESIN Rising
RHOX
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Not tested
4 Not applicable to latched A2 1 These signals change only on falling T
5 For write cycle followed by read cycle
6 Operating conditions for 25 MHz are 0 C to
(Continued)
Parameter
70 C V
5 0V
a
e
CC
80C186EA 80C188EA 80L186EA 80L188EA
Min
Max
T
15
b
T
10
b
T
10
b
T
10
b
T
15
b
T
15
b
T
10
b
T
10
b
0
(2 T)
5
b
(2 T)
5
b
T
15
b
T
15
b
T
10
b
T
10
b
T
10
b
T
10
b
0
T
T
1
10%
g
Unit
Notes
ns
ns
ns
1
ns
ns
1
ns
1
ns
1
ns
1
ns
ns
2
ns
2
ns
ns
ns
1
ns
1 4
ns
1 4
ns
1
ns
5
ns
3
ns
3
29
29
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