Intel 80C186EA Preliminary Information page 10

80C186EA 80C188EA 80L186EA 80L188EA
Symbol
P
G
I
O
I O
S(E)
S(L)
A(E)
A(L)
H(1)
H(0)
H(Z)
H(Q)
H(X)
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
I(1)
I(0)
I(Z)
I(Q)
I(X)
P(1)
P(0)
P(Z)
P(Q)
P(X)
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Table 2 Pin Description Nomenclature
Power Pin (Apply
a
Ground (Connect to V
Input Only Pin
Output Only Pin
Input Output Pin
Synchronous Edge Sensitive
Synchronous Level Sensitive
Asynchronous Edge Sensitive
Asynchronous Level Sensitive
Output Driven to V
Output Driven to V
Output Floats during Bus Hold
Output Remains Active during Bus Hold
Output Retains Current State during Bus Hold
Output Weakly Held at V
Output Driven to V
Output Driven to V
Output Floats during Reset
Output Remains Active during Reset
Output Retains Current State during Reset
Output Driven to V
Output Driven to V
Output Floats during Idle Mode
Output Remains Active during Idle Mode
Output Retains Current State during Idle Mode
Output Driven to V
Output Driven to V
Output Floats during Powerdown Mode
Output Remains Active during Powerdown Mode
Output Retains Current State during Powerdown Mode
Description
V Voltage)
CC
)
SS
during Bus Hold
CC
during Bus Hold
SS
during Reset
CC
during Reset
CC
during Reset
SS
during Idle Mode
CC
during Idle Mode
SS
during Powerdown Mode
CC
during Powerdown Mode
SS
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