Intel 80C186EA Preliminary Information page 45

INSTRUCTION SET SUMMARY
Function
DATA TRANSFER (Continued)
SEGMENT Segment Override
e
CS
SS
DS
ES
ARITHMETIC
ADD Add
e
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
ADC Add with carry
e
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
INC Increment
e
Register memory
Register
SUB Subtract
e
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
SBB Subtract with borrow
e
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
DEC Decrement
e
Register memory
Register
CMP Compare
e
Register memory with register
Register with register memory
Immediate with register memory
Immediate with accumulator
Change sign register memory
NEG
e
AAA ASCII adjust for add
e
DAA Decimal adjust for add
e
AAS ASCII adjust for subtract
e
DAS Decimal adjust for subtract
e
MUL Multiply (unsigned)
e
Register-Byte
Register-Word
Memory-Byte
Memory-Word
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
80C186EA 80C188EA 80L186EA 80L188EA
(Continued)
Format
0 0 1 0 1 1 1 0
0 0 1 1 0 1 1 0
0 0 1 1 1 1 1 0
0 0 1 0 0 1 1 0
0 0 0 0 0 0 d w mod reg r m
1 0 0 0 0 0 s w mod 0 0 0 r m
0 0 0 0 0 1 0 w data data if w
0 0 0 1 0 0 d w mod reg r m
1 0 0 0 0 0 s w mod 0 1 0 r m
0 0 0 1 0 1 0 w data data if w
1 1 1 1 1 1 1 w mod 0 0 0 r m
0 1 0 0 0 reg
0 0 1 0 1 0 d w mod reg r m
1 0 0 0 0 0 s w mod 1 0 1 r m
0 0 1 0 1 1 0 w data data if w
0 0 0 1 1 0 d w mod reg r m
1 0 0 0 0 0 s w mod 0 1 1 r m
0 0 0 1 1 1 0 w data data if w
1 1 1 1 1 1 1 w mod 0 0 1 r m
0 1 0 0 1 reg
0 0 1 1 1 0 1 w mod reg r m
0 0 1 1 1 0 0 w mod reg r m
1 0 0 0 0 0 s w mod 1 1 1 r m
0 0 1 1 1 1 0 w data data if w
1 1 1 1 0 1 1 w mod 0 1 1 r m
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
1 1 1 1 0 1 1 w mod 100 r m
80C186EA
Clock
Cycles
2
2
2
2
3 10
data data if s w 01 4 16
e
1 3 4
e
3 10
data data if s w 01 4 16
e
1 3 4
e
3 15
3
3 10
data data if s w 01 4 16
e
1 3 4
e
3 10
data data if s w 01 4 16
e
1 3 4
e
3 15
3
3 10
3 10
data data if s w 01 3 10
e
1 3 4
e
3 10
8
4
7
4
26–28
35–37
32–34
41–43
80C188EA
Comments
Clock
Cycles
2
2
2
2
3 10
4 16
3 4 8 16-bit
3 10
4 16
3 4 8 16-bit
3 15
3
3 10
4 16
3 4 8 16-bit
3 10
4 16
3 4 8 16-bit
3 15
3
3 10
3 10
3 10
3 4 8 16-bit
3 10
8
4
7
4
26–28
35–37
32–34
41–48
45
45