Intel 80C186EA Preliminary Information page 48

16-bit high-integration embedded processors
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80C186EA 80C188EA 80L186EA 80L188EA
INSTRUCTION SET SUMMARY
Function
CONTROL TRANSFER (Continued)
RET
Return from CALL
e
Within segment
Within seg adding immed to SP
Intersegment
Intersegment adding immediate to SP
JE JZ
Jump on equal zero
e
JL JNGE
Jump on less not greater or equal
e
JLE JNG
Jump on less or equal not greater
e
JB JNAE
Jump on below not above or equal
e
JBE JNA
Jump on below or equal not above
e
JP JPE
Jump on parity parity even
e
JO
Jump on overflow
e
JS
Jump on sign
e
JNE JNZ
Jump on not equal not zero
e
JNL JGE
Jump on not less greater or equal
e
JNLE JG
Jump on not less or equal greater
e
JNB JAE
Jump on not below above or equal
e
JNBE JA
Jump on not below or equal above
e
JNP JPO
Jump on not par par odd
e
JNO
Jump on not overflow
e
JNS
Jump on not sign
e
JCXZ
Jump on CX zero
e
LOOP
Loop CX times
e
LOOPZ LOOPE
Loop while zero equal
e
LOOPNZ LOOPNE
Loop while not zero equal
e
ENTER
Enter Procedure
e
L
0
e
L
1
e
L
1
l
LEAVE
Leave Procedure
e
INT
Interrupt
e
Type specified
Type 3
INTO
Interrupt on overflow
e
IRET
Interrupt return
e
BOUND
Detect value out of range
e
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
48
(Continued)
Format
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
data-low
data-high
1 1 0 0 1 0 1 1
1 1 0 0 1 0 1 0
data-low
data-high
0 1 1 1 0 1 0 0
disp
0 1 1 1 1 1 0 0
disp
0 1 1 1 1 1 1 0
disp
0 1 1 1 0 0 1 0
disp
0 1 1 1 0 1 1 0
disp
0 1 1 1 1 0 1 0
disp
0 1 1 1 0 0 0 0
disp
0 1 1 1 1 0 0 0
disp
0 1 1 1 0 1 0 1
disp
0 1 1 1 1 1 0 1
disp
0 1 1 1 1 1 1 1
disp
0 1 1 1 0 0 1 1
disp
0 1 1 1 0 1 1 1
disp
0 1 1 1 1 0 1 1
disp
0 1 1 1 0 0 0 1
disp
0 1 1 1 1 0 0 1
disp
1 1 1 0 0 0 1 1
disp
1 1 1 0 0 0 1 0
disp
1 1 1 0 0 0 0 1
disp
1 1 1 0 0 0 0 0
disp
1 1 0 0 1 0 0 0
data-low
data-high
1 1 0 0 1 0 0 1
1 1 0 0 1 1 0 1
type
1 1 0 0 1 1 0 0
1 1 0 0 1 1 1 0
1 1 0 0 1 1 1 1
0 1 1 0 0 0 1 0
mod reg r m
80C186EA
80C188EA
Clock
Clock
Cycles
Cycles
16
20
18
22
22
30
25
33
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
4 13
5 15
5 15
6 16
6 16
taken LOOP
6 16
6 16
6 16
6 16
L
15
19
25
29
22
16(n
1)
26
20(n
1)
a
b
a
b
8
8
47
47
45
45
if INT taken
48 4
48 4
28
28
33–35
33–35
Comments
JMP not
taken JMP
taken
LOOP not
taken
if INT not
taken
48

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