Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications; Front Side Bus And Gtlref; Power And Ground Lands - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
2
Dual-Core Intel® Xeon®
Processor 5200 Series Electrical
Specifications
2.1

Front Side Bus and GTLREF

Most Dual-Core Intel® Xeon® Processor 5200 Series FSB signals use Assisted Gunning
Transceiver Logic (AGTL+) signaling technology. This technology provides improved
noise margins and reduced ringing through low voltage swings and controlled edge
rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high
logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the
addition of an active PMOS pull-up transistor to "assist" the pull-up resistors during the
first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as V
power planes for each processor (and chipset), separate V
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to
The AGTL+ inputs require reference voltages (GTLREF_DATA and GTLREF_ADD) which
are used by the receivers to determine if a signal is a logical 0 or a logical 1.
GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is
used for the 2X and common clock front side bus signaling groups. Both GTLREF_DATA
and GTLREF_ADD must be generated on the baseboard (See
GTLREF_DATA and GTLREF_ADD specifications). Refer to the applicable platform design
guidelines for details. Termination resistors (R
processor silicon and are terminated to V
enabled on the Dual-Core Intel® Xeon® Processor 5200 Series to control reflections on
the transmission line. Intel chipsets also provide on-die termination, thus eliminating
the need to terminate the bus on the baseboard for most AGTL+ signals.
Some FSB signals do not include on-die termination (R
the baseboard. See
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the Dual-Core
Intel® Xeon® Processor 5200 Series signal integrity models, which includes buffer and
package models.
2.2

Power and Ground Lands

For clean on-chip processor core power distribution, the processor has 223 V
and 273 V
plane, while all V
processor V
Voltage IDentification (VID) signals. See
Table 2-8 for details regarding these signals.
(ground) inputs. All V
SS
lands must be connected to the system ground plane. The
SS
lands must be supplied with the voltage determined by the processor
CC
. Because platforms implement separate
TT
Section
) for AGTL+ signals are provided on the
TT
. The on-die termination resistors are always
TT
) and must be terminated on
TT
lands must be connected to the processor power
CC
Table 2-3 for VID definitions.
and V supplies are
CC TT
1.3).
Table 2-18 for
(power)
CC
15