DMD2050E Univeral Satellite Modem
6.3
Alarms
6.3.1
Major Transmit Alarms
Alarm
FPGA CFG
DSP CFG
SCT Clock PLL
SYM Clock PLL
LB Synth PLL
IF Synth PLL
Forced Alarm
Ethernet WAN
TRANSEC NOT RDY
6.3.2
Major Rx Alarms
Alarm
FPGA CFG
DSP CFG
SIGNAL LOCK
MN-DMD2050E Revision 2
Description
A transmit FPGA hardware failure exists.
A transmit FPGA failure exists.
The Tx SCT Clock PLL is not locked. This alarm flashes on
during certain parameter changes. If the alarm is on constantly,
there is a configuration problem within the modem.
The Tx Symbol Clock PLL is not locked. This alarm flashes on
during certain parameter changes. If the alarm is on constantly,
there is a configuration problem with the incoming clock to the
modem (SCTE).
The Tx L-Band Synthesizer is not locked. This alarm flashes on
during certain parameter changes. If the alarm is on constantly,
there is a configuration problem within the modem.
The Tx IF Synthesizer is not locked. This alarm flashes on
during certain parameter changes. If the alarm is on constantly,
there is a configuration problem within the modem.
Allows the user to disable or enable forcing of the Tx summary
alarm.
The WAN Port is not operating.
This alarm is acgtive during the time that the TRANSEC card is
booting
Description
A receive FPGA hardware failure exists.
A receive DSP failure exists.
The demod cannot lock to a signal.
Maintenance and Troubleshooting
Status
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{DISABLED,
ENABLED}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
Status
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
{Pass/Fail,
Unmasked/Masked}
6–3
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