The Hsmb Tab - Intel Cyclone V GT FPGA Development Kit User Manual

• Pre—Not available.
— First post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
Second post—Not available.
• Equalizer—Specifies the setting for the receiver equalizer.
• DC gain—Specifies the DC portion of the receiver equalizer.
Data Type—Specifies the type of data contained in the transactions. The following
data types are available for analysis:
• PRBS7—Pseudo-random 7-bit sequences
• PRBS15—Pseudo-random 15-bit sequences
• PRBS23—Pseudo-random 23-bit sequences
• PRBS31—Pseudo-random 31-bit sequences
•
HF—Highest frequency divide-by-4 data pattern
•
LF—Lowest frequency divide-by-4 data pattern

6.3.7. The HSMB Tab

HSMB stands for high-speed mezzanine card for Port B.
The HSMB tab as shown in the following figure allows you to perform loopback tests
on the HSMB transceiver (XCVR) and HSMB CMOS ports.
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Cyclone V GT FPGA Development Kit User Guide
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6. Board Test System
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