Development Board Setup; Setting Up The Board - Intel Cyclone V GT FPGA Development Kit User Manual

792833 | 2024.02.21
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4. Development Board Setup

This chapter explains how to set up the Cyclone V GT FPGA development board and
restore default settings.

4.1. Setting Up the Board

Following are the steps to configure and apply power to the board:
1. The FPGA development board ships with its board switches preconfigured to
support the design examples in the kit. If your board might not be currently
configured with the default settings, follow the instructions in Factory Default
Switch and Jumper Settings before proceeding.
2. The FPGA development board ships with design examples stored in flash memory.
Verify the SW4.3 DIP switch is set to the FACT ON (logic 0) position to load the
design stored in the factory portion of flash memory.
The FPGA development board can be powered by the PCIe* host adapter or the laptop
power adapter. If you want to power the board by the PCIe host system, plug the
FPGA development card into a standard PCIe connector. Alternatively, to power the
FPGA development board using the laptop power adaptor, perform the following two
steps:
1. Connect the +19 V (6.32 A) power supply to the DC Power Jack (J8) on the FPGA
board and plug the cord into a power outlet.
Use only the supplied power supply. Power regulation circuitry on the board can be
damaged by power supplies with greater voltage, and a lower-rated power supply
may not be able to provide enough power for the board.
2. Set the POWER switch (SW2) to the ON position. When power is supplied to the
board, blue LED (D21) illuminates indicating that the board has power.
The MAX
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The SW4.3 DIP switch controls which design to
load. When the switch is in the FACT ON (logic 0) position, the PFL loads the design
from the factory portion of flash memory.
The MAX V design resides in the
\cycloneVGT_5cgtfd9ef35_fpga\examples\max5
When configuration is complete, the Config Done LED (D7) illuminates, signaling that
the Cyclone V GT device configured successfully.
For more information about the PFL megafunction, refer to the Parallel Flash Loaded
Megafunction User Guide.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
®
V device on the board contains (among other things) a parallel flash loader
<install dir>\kits
directory.
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