Clock Control Features; Clock Control Controls - Intel Cyclone V GT FPGA Development Kit User Manual

6. Board Test System
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6.5.1. Clock Control Features

The Clock Control application sets the Si570 and Si571 programmable oscillators to
any frequency between 10 MHz and 810 MHz.
• The Si570 (not the Si571) oscillator drives a 1-to-6 buffer that drives a copy of the
clock to the following areas of the FPGA:
— Top, bottom, and right edges
— REFCLK0 and REFCLK3
• The 6th clock outputs to SMAs J4 and J7 on the board.
• The Clock Control communicates with the MAX V device on the board through the
JTAG bus.
• The Si570 and Si571 programmable oscillators are connected to the MAX V device
through a 2-wire serial bus.
The following figure shows the Clock Control Si570 tab, which has the same controls
as the Si571 tab.
Figure 15. The Clock Control - Si570 Tab

6.5.2. Clock Control Controls

The following sections describe the Clock Control controls.
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Cyclone V GT FPGA Development Kit User Guide
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