Intel Cyclone V GT FPGA Development Kit User Manual page 31

6. Board Test System
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Figure 11. The DDR3x64 Tab
The following sections describe the controls on the DDR3x40 and DDR3x64 tabs.
6.3.5.1. Start
Initiates DDR3 memory transaction performance analysis.
6.3.5.2. Stop
Terminates the transaction performance analysis.
6.3.5.3. Performance Indicators
Display current transaction performance analysis information collected since you last
clicked Start:
• Write, Read, and Total performance bars—Show the percentage of the
maximum theoretical data rate that the requested transactions are able to
achieve.
• Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of
data analyzed per second.
— DDR3x40—The theoretical maximum bandwidth is 3200 MBps.
— DDR3x64—The theoretical maximum bandwidth is 4800 MBps.
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Cyclone V GT FPGA Development Kit User Guide
31