Intel Arria 10 User Manual page 102

Instruction
(8bits)
00000101
00000110
00000111
00001001
00001011
® ®
Intel Arria
102
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Instruction
Description
Read HPS Push Register 2:
Button and DIP
Current Status of USER_PB_HPS and USER_DIPSW_HPS
switch registers
Bit[7:4] - USER_PB_HPS [3:0]
Bit[3:0] - USER_DIPSW_HPS [3:0]
Write HPS Push Register 3:
Button IRQ flag
Bit[7] - Write logic one to clear bit 7 flag in register 2, write logic zero to reset this bit
clear registers
after the flag is cleared
Bit[6] - Write logic one to clear bit 6 flag in register 2, write logic zero to reset this bit
after the flag is cleared
Bit[5] - Write logic one to clear bit 5 flag in register 2 , write logic zero to reset this
bit after the flag is cleared
Bit[4] - Write logic one to clear bit 4 flag in register 2 , write logic zero to reset this
bit after the flag is cleared
Read HPS Push Register 3: Read-only Register
Button IRQ flag
Bit[7:4] - USER_PB_HPS hold registers bits
Registers
Bit 7: USER_PB_HPS3 IRQ Flag, active low, clear flag by register 3 bit 7.
Bit 6: USER_PB_HPS2 IRQ Flag, active low, clear flag by register3 bit 6.
Bit 5: USER_PB_HPS1 IRQ Flag, active low, clear flag by register3 bit 5.
Bit 4: USER_PB_HPS0 IRQ Flag, active low, clear flag by register3 bit 4.
Bit[3:0] - reserved
If one of the push buttons is pressed, the corresponding PB's IRQ register bit is set
and A10_SH_GPIO0 is configured to '0'.
The A10_SH_GPIO0 returns to '1' after the HPS clears the associated bit (even if the
PB is still held down).
If the second push button is pressed while the HPS is handling the first push button
interrupt, the second PB's IRQ register bit remains as a '0' until HPS clears the
interrupt. A10_SH_GPIO0 stays low until the HPS clears the second PB's IRQ register
bit.
Read Power good1 Register 4: Read-only register
Registers
Bit[7] - operation_flag. '1': Power on finished. '0': The system is in Power down cycle
Bit[6] - 1V8_Pgood. '1':1.8V power rail output is normal. '0':1.8V power rail output is
abnormal.
Bit[5] - 2V5_Pgood. '1':2.5V power rail output is normal. '0':2.5V power rail output is
abnormal.
Bit[4] - 3V3_Pgood. '1':3.3V power rail output is normal. '0':3.3V power rail output is
abnormal.
Bit[3] - 5V0_Pgood. '1':5V power rail output is normal. '0':5V power rail output is
abnormal.
Bit[2] - 0V9_Pgood. '1':0.9V power rail output is normal. '0': 0.9V power rail output is
abnormal.
Bit[1] - 0V95_Pgood. '1':0.95V power rail output is normal. '0': 0.95V power rail
output is abnormal.
Bit[0] - 1V0_Pgood. '1':1.0V power rail output is normal. '0': 1.0V power rail output is
abnormal.
Read Power good2 Register 5: Read-only register
Registers
Bit[7] - HPS_Pgood. '1': HPS core power rail output is normal. '0': HPS core power rail
output is abnormal.
Bit[6] - HILOHPS_VDDPgood. '1':HPS memory power rail output is normal. '0': HPS
memory power rail output is abnormal.
Bit[5] - HILO_VDDPgood. '1':FPGA memory VDD power rail output is normal. '0':
FPGA memory VDD power rail output is abnormal.
Bit[4] - HILO_VDDQPgood . '1': FPGA memory VDDQ power rail output is normal. '0':
FPGA memory VDDQ power rail output is abnormal.
Bit[3] - FMCAVADJPGood. '1':FMCAVADJ power rail output is normal. '0': FMCAVADJ
power rail output is abnormal.
10 SoC Development Kit User Guide
Register Data Description
5. Board Components
683227 | 2023.07.12
continued...
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