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5.9.12. HPS SPIO Interface
Table 50.
Pin
nCS
Chip Select
SCK
Serial Clock
MOSI
Serial Data Input
MISO
Serial Data output
Figure 31.
Figure 32.
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Intel
Arria
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Arrow.com.
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The HPS can monitor and control the following functional signals through the SPI
interface:
•
HPS LED signals
•
HPS Push button and DIP switch signals
•
Power good and present signals
•
Reset signals
•
FMCA/B PCIE power enable signals
•
SFP+ control signals
2
•
I
C master indication signal
•
HPS warm reset signals
•
PMBUS control signals
SPI Interface Pin Definition
Description
Active low signal that enables the slave device to receive or transfer data from the master
device
The clock signal produced from the master device to synchronize the data transfer
Receive data serially at the positive SCK clock.
Transmit data serially at the negative SCK clock edge.
The HPS SPI controller is the SPI master, and the MAX V works as a slave SPI I/O
expander. The SPI interface uses 8-bit frame size. For MOSI, the first byte is used as
an instruction byte. Bit [7:1] is the register address. Bit [0] is the operation flag
where logic '1' is read flag and logic '0' is the write flag. The second byte is the data
byte. For MISO, the first byte are zero byte (pad), second byte is the data byte.
HPS SPI Controller Write Timing Diagram
Write Instruction
SCK
CSn
MOSI
MISO
HPS SPI Write Timing (Write/Write)
Write followed by Write
In transaction 1 a write instruction (I1) is sent with accompanying data and the read data from a prior instruction is returned .
In transaction 2 a write instruction (I2) is sent with accompanying data and the read data from a prior instruction is returned .
10 SoC Development Kit User Guide
Function
1
2
3
4
5
6
7
8
9
10
MSB
0
Register#
Data to store in Register#
Instruction
0
0
0
0
0
0
0
0
zeros
I1(write)
WD1
I2(write)
0
0
0
5. Board Components
683227 | 2023.07.12
11
12
13
14
15
16
LSB
0
zeros
WD2
0
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