10/100/1000 Ethernet (Fpga) - Intel Arria 10 User Manual

5.9.3. 10/100/1000 Ethernet (FPGA)

Figure 27.
Table 32.
FPGA Pin Assignment
AK38
AK39
AG32
AG33
AL36
AL37
AH34
AH35
AG29
AG28
® ®
Intel Arria
74
Arrow.com.
Downloaded from
The development board supports two RJ45 10/100/1000 base-T Ethernet using Marvell
88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.
MII Interface between FPGA (MAC) and PHY
(1E,0)
FPGA SGMII
MAC
(1E,1)
Ethernet (FPGA) Pin Assignments
Schematic Signal Name
ENETA_TX_N
ENETA_TX_P
ENETA_RX_N
ENETA_RX_P
ENETB_TX_N
ENETB_TX_P
ENETB_RX_N
ENETB_RX_P
CLK_ENET_FPGA_P
CLK_ENET_FPGA_N
10 SoC Development Kit User Guide
MARVELL
88E1111 SGMII
PHY
MARVELL
88E1111 SGMII
PHY
Direction
Output
Output
Input
Input
Output
Output
Input
Input
Input
Input
5. Board Components
683227 | 2023.07.12
Port 1
RJ-45
Port 2
RJ-45
Description
Ethernet Port A Transmitter
Ethernet Port A Transmitter
Ethernet Port A Receiver
Ethernet Port A Receiver
Ethernet Port B Transmitter
Ethernet Port B Transmitter
Ethernet Port B Receiver
Ethernet Port B Receiver
125MHz Reference clock
from Clock Synthesizer
125MHz Reference clock
from Clock Synthesizer
Send Feedback