Clock Circuits; On-Board Oscillators - Intel Stratix 10 GX FPGA User Manual

4.7. Clock Circuits

4.7.1. On-Board Oscillators

Figure 11.
Table 31.
Source
U7
® ®
Intel Stratix
46
Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from
Intel Stratix 10 GX FPGA Board - Clock Inputs and Default Frequencies
REFCLK1 (155.52 MHz LVDS)
OUT0
REFCLK_QSFPI1 (644.53125 MHz LVDS)
OUT1
REFCLK_DP (135 MHz LVDS)
OUT2
OUT3
REFCLK4 (156.25 MHz LVDS)
Si5341A OUT4
REFCLK_FMCA (625 MHz LVDS)
(U7) OUT5
OUT6
CLK_ENET (125 MHz LVDS)
OUT7
MAXV_OSC_CLK1 (125 MHz)
OUT8
CLK_CONFIG (125 MHz LVDS)
OUT9
MAX V MAXV_OSC_CLK1 (125 MHz LVCMOS)
(U11) CLK_MAXV_50M (50 MHz LVCMOS)
OUT3
CLK_HILO (133 MHz LVDS)
Si5338A
OUT2
CLK_FPGA_B3L (100 MHz LVDS)
(U9)
OUT1
PCIE_OB_REFCLK (100 MHz)
OUT0
On-Board Oscillators
Schematic Signal
Name
REFCLK1_P
REFCLK1_N
REFCLK_QSFP1_P
REFCLK_QSFP1_N
REFCLK_DP_P
REFCLK_DP_N
REFCLK4_P
REFCLK4_N
REFCLK_FMCA_P
REFCLK_FMCA_N
CLK_ENET_P
CLK_ENET_N
10 GX FPGA Development Kit User Guide
Frequency I/O Standard
LVDS
155.52 MHz
LVDS
LVDS
644.53125 MHz
LVDS
LVDS
135 MHz
LVDS
LVDS
156.25 MHz
LVDS
LVDS
625 MHz
LVDS
LVDS
125 MHz
LVDS
4. Board Components
UG-20046 | 2020.04.02
4C 4D 4E 4F 4K 4L 4M 4N
2A
CLK_FPGA_50M
2B
Intel
(50 MHz LVCMOS)
2C
Stratix 10
2F
FPGA (U1)
2L
2M
2N
FPGA_OSC_CLK1
OSC_CLK_1 (Configuration Clock)
(125 MHz LVCMOS)
1C 1D 1E 1F 1K 1L 1M 1N
REFCLK_SDI
(148.5 MHz LVDS)
Intel Stratix 10 Application
FPGA Pin Number
AM41
Transceiver
reference clocks
AM40
Y38
QSFP reference
Y37
AK38
DisplayPort
reference clocks
AK37
AF9
Transceiver
reference clocks
AF10
AT9
FMC reference
AT10
AN27
Ethernet clock
AN28
Send Feedback
3A
3B
3C
3I
3J
3K
3L
Si516 (X1)
Bank 1D
clocks
Bank 4E
clocks
continued...