Intel Arria 10 User Manual page 37

Soc development kit
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4. Board Test System
683227 | 2023.07.12
Port
PMA Setting
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Details—Shows the PLL lock and pattern sync status:
Allows you to specify which interface to test. The following port tests are
available:
XCVR
CMOS
Allows you to make changes to the PMA parameters that affect the active
transceiver interface. The following settings are available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver.
VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap
Equalizer—Specifies the AC gain setting for the receiver equalizer in four
stage mode.
DC gain—Specifies the DC gain setting for the receiver equalizer in four
stage mode.
VGA—Specifies the VGA gain value.
Description
1st pre—Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
2nd pre—Specifies the amount of pre-emphasis on the second pre-tap
of the transmitter buffer.
1st post—Specifies the amount of pre-emphasis on the first post tap of
the transmitter buffer.
2nd post—Specifies the amount of pre-emphasis on the second post
tap of the transmitter buffer.
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10 SoC Development Kit User Guide
37

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