Intel Arria 10 User Manual page 56

I/O Bank Board Reference
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2
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® ®
Intel Arria
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R13 RESET_HPS_UARTA_N
R12 MAX2toMAXV0
P11 MAX2toMAXV1
N12 MAX2toMAXV2
R14 MAX2toMAXV3
P12 MAX2toMAXV4
T15 MAX2toMAXV5
R16 MAX2toMAXV6
P13 MAX2toMAXV7
M11 MAX2toMAXV8
M12 MAX2toMAXV9
N9 MAX2toMAXV10
R4 MAX2toMAXV11
T10 MAX2toMAXV12
T4 MAX2toMAXV13
D4 USER_LED_FPGA0
B1 USER_LED_FPGA1
C5 USER_LED_FPGA2
C4 USER_LED_FPGA3
B4 USER_LED_HPS0
D6 USER_LED_HPS1
E6 USER_LED_HPS2
B5 USER_LED_HPS3
A5 MAX_ERROR
D7 MAX_LOAD
10 SoC Development Kit User Guide
Pin Name Pin Type
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
OC
OC
OC
OC
OC
OC
OC
OC
OC
OC
5. Board Components
683227 | 2023.07.12
I/O Description
Standa
rd
this high after
PCIE_EN
active. PCIe RC slot reset,
active low.
3.3 V UART_RESET (Active low)
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbusbetween MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
3.3 V Interbus between MAX II
and MAX V
2.5 V USER FPGA LED 0 output
2.5 V USER FPGA LED 1 output
2.5 V USER FPGA LED 2 output
2.5 V USER FPGA LED 3 output
2.5 V HPS LED 0 output
2.5 V HPS LED 1 output
2.5 V HPS LED 2 output
2.5 V HPS LED 3 output
2.5 V Board abnormal indicator
2.5 V FPGA status LED
continued...
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