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5. Board Components
683227 | 2023.07.12
I/O Bank Board Reference
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Pin Name
P7
SFPA_RATESEL0
R6
SFPA_RATESEL1
N7
SFPB_TXDISABLE
M7
SFPB_RATESEL0
R7
SFPB_RATESEL1
P8
SFPB_LOS
T7
SFPB_TXFAULT
N8
SFPA_MOD0_PRSNTn
R8
SFPB_MOD0_PRSNTn
T8
NC
T9
NC
R9
Eneta_HPS_Intn
M9
Logic_resetn
M8
EXT_intn
M10
UART1_RX
R10
UART1_TX
N10
NC
T11
LMK_reset
P10
NC
R11
NC
T12
ENET_HPS_RESETn
N11
USB_RESET
T13
PCIE_PERSTn
Pin Type
I/O
Standa
rd
Output
3.3 V
SFP+ A RX signaling rate
selection, 0<4.25 GBd, 1 >
4.25 GBd
Output
3.3 V
SFP +A TX signaling rate
selection, 0<4.25 GBd, 1 >
4.25 GBd
Output
3.3 V
SFP+ B socket TX disable
signal. Active low
Output
3.3 V
SFP+ B RX signaling rate
selection, 0<4.25 GBd, 1 >
4.25 GBd
Output
3.3 V
SFP +B TX signaling rate
selection, 0<4.25 GBd, 1 >
4.25 GBd
Input
3.3 V
SFP+ A socket loss signal
(Active low)
Input
3.3 V
SFP+ A socket tx fault
signal (Active low)
Input
3.3 V
Detect signal of SFP+
module in slot A (Active
low)
Input
3.3 V
Detect signal of SFP+
module in Slot B. (Active
low)
-
3.3 V
-
-
3.3 V
-
Input
3.3 V
Interrupt input from
Ethernet port 3
Input
3.3 V
FPGA_logic reset input
Input
3.3 V
HPS External interrupt
Input
3.3 V
DB9 RS232 UART RX
Output
3.3 V
DB9 RS232 UART TX
Output
3.3 V
-
Output
3.3 V
LMK Clock cleaner reset
(Active high)
-
3.3 V
-
-
3.3 V
-
Output
3.3 V
Ethernet port 3 reset
(Active low)
Output
3.3 V
USB PHY reset (Active
high)
Output
3.3 V
This signal needs to be
held low if
and
PCIE_EN
active. 15 ms delay to set
®
®
Intel
Arria
10 SoC Development Kit User Guide
Description
PCIE_auxEn
are not
continued...
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