NEC mPD784225 Series User Manual page 475

Table 24-3. Releasing HALT Mode and Operation After Release
Note 1
Release Source MK
×
RESET input
×
NMI pin input
0
Maskable
interrupt
request (except
for a macro
service request)
0
1
Macro service 0
request
1
Notes 1. Interrupt mask bit in each interrupt request source
2. Interrupt enable flag in the program status word (PSW)
3. The pending interrupt request is acknowledged when acknowledgement is enabled.
4. Bit in the interrupt mode control register (IMC)
5. Bit in the macro service mode register of the macro service control word that is in each macro service
request source
CHAPTER 24 STANDBY FUNCTION
Note 2
IE State During Release
×
×
• None while executing a non-maskable
interrupt service program
• Executing a low-priority non-maskable
interrupt service program
• Executing the service program for
the same request
• Executing a high-priority non-maskable
interrupt service program
1 • None while executing an interrupt
service program
• Executing a low-priority maskable
interrupt service program
Note 4
• The PRSL bit
0 while executing an interrupt
service program at priority level 3.
• Executing a maskable interrupt
service program with the same
priority
(This excludes executing an interrupt
service program in priority level 3
when the PRSL bit
to 0.)
• Executing a high-priority interrupt
service program
0
×
×
×
User's Manual U12697EJ3V0UM
– Normal reset operation
Acknowledges interrupt requests
The instruction following the MOV
STBC, #byte instruction is executed.
(The interrupt request that released
the HALT mode is held pending
Acknowledges interrupt requests
is cleared to
The instruction following MOV STBC,
#byte is executed.
(The interrupt request that released
the HALT mode is held pending
Note 4
is cleared
–
– Holds the HALT mode
– Macro service process execution
End condition is not satisfied → End
HALT mode condition is satisfied
again
→ When VCIE
When VCIE
– Holds the HALT mode
Operation After Release
3
.)
Note 3
Note 5
= 1:
HALT mode again
Note 5
= 0:
Same as a release by the
maskable interrupt request
475
.)