NEC mPD784225 Series User Manual page 352

19.2 Configuration
The clock output function includes the following hardware.
Control registers
f
XX
f /2
XX
2
f /2
XX
3
f /2
XX
4
f /2
XX
f /2 5
XX
6
f /2
XX
f /2 7
XX
f
XT
CLOE CCS3 CCS2 CCS1 CCS0
19.3 Control Registers
The following two registers are used to control the clock output function.
• Clock output control register (CKS)
• Port 2 mode register (PM2)
(1) Clock output control register (CKS)
This register sets the PCL output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CKS to 00H.
Remark CKS provides a function for setting the buzzer output clock besides setting the PCL output clock.
352
CHAPTER 19 CLOCK OUTPUT FUNCTION
Table 19-1. Configuration of Clock Output Function
Item
Clock output control register (CKS)
Port 2 mode register (PM2)
Figure 19-2. Block Diagram of Clock Output Function
Synchronization
circuit
4
Clock output control register (CKS)
Internal Bus
User's Manual U12697EJ3V0UM
Configuration
P23 output latch
PM23
Port 2 mode register (PM2)
PCL/P23