Table of Contents
Advertisement
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
INTP3/P03
3
ADCS
TRG FR2 FR1 FR0 EGA1 EGA0 ADCE
ADIS2 ADIS1 ADIS0
A/D converter input
selection register (ADIS)
Note
Valid edge specified with bit 3 (EGP3, EGN3) of external interrupt rising edge/falling edge enable registers
0 (EGP0, EGN0) (Refer to Figure 21-1 Format of External Interrupt Rising Edge Enable Register 0
(EGP0) and External Interrupt Falling Edge Enable Register 0 (EGN0)).
CHAPTER 13 A/D CONVERTER
Figure 13-1. Block Diagram of A/D Converter
Sample & hold circuit
Edge
detector
Edge
detector
Note
Trigger enable
A/D converter
mode register (ADM)
Internal bus
User's Manual U12697EJ3V0UM
Voltage
comparator
Successive
approximation
register (SAR)
Controller
A/ D conversion
result register
(ADCR)
AV
DD
AV
SS
INTAD
INTP3
231
Advertisement
Table of Contents
