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CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(b) Asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2)
ASIS1 and ASIS2 can be read by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIS1 and ASIS 2 to 00H.
Address: 0FF72H, 0FF73H After reset: 00H
Symbol
7
ASISn
0
PEn
FEn
OVEn
Notes 1. Even if the stop bit length has been set to 2 bits with bit 2 (SLn) of asynchronous serial interface
mode register n (ASIMn), stop bit detection during reception is only 1 bit.
2. Be sure to read receive buffer register n (RXBn) when an overrun error occurs.
An overrun error is generated each time data is received until RXBn is read.
Remark n = 1, 2
R
6
5
4
0
0
0
0
Parity error not generated
1
Parity error generated
(when parity of transmit data does not match)
0
Framing error not generated
1
Framing error generated
(when stop bit(s) is not detected)
0
Overrun error not generated
1
Overrun error generated
(When next receive operation is completed before data from receive buffer
register is read)
User's Manual U12697EJ3V0UM
3
2
0
PEn
Parity error flag
Framing error flag
Note 1
Overrun error flag
Note 2
1
0
FEn
OVEn
271
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