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Figure No.
8-28
Timing of One-Shot Pulse Output Operation by External Trigger (with Riding Edge Specified) .......
8-29
Start Timing of 16-Bit Timer Counter 0 .............................................................................................
8-30
Timing After Changing Compare Register During Timer Count Operation .......................................
8-31
Data Hold Timing of Capture Register ..............................................................................................
8-32
Operation Timing of OVF0 Flag ........................................................................................................
9-1
Block Diagram of 8-Bit Timer/Event Counters 1 and 2 .....................................................................
9-2
Format of 8-Bit Timer Mode Control Register 1 (TMC1) ...................................................................
9-3
Format of 8-Bit Timer Mode Control Register 2 (TMC2) ...................................................................
9-4
Format of Prescaler Mode Register 1 (PRM1) .................................................................................
9-5
Format of Prescaler Mode Register 2 (PRM2) .................................................................................
9-6
Timing of Interval Timer Operation ....................................................................................................
9-7
Timing of External Event Counter Operation (When Rising Edge Is Set) .........................................
9-8
Timing of PWM Output ......................................................................................................................
9-9
Timing of Operation Based on CRn0 Transitions ..............................................................................
9-10
Cascade Connection Mode with 16-Bit Resolution ...........................................................................
9-11
Start Timing of 8-Bit Timer Counter ..................................................................................................
9-12
Timing After Compare Register Changes During Timer Counting ....................................................
10-1
Block Diagram of 8-Bit Timers 5 and 6 .............................................................................................
10-2
Format of 8-Bit Timer Mode Control Register 5 (TMC5) ...................................................................
10-3
Format of 8-Bit Timer Mode Control Register 6 (TMC6) ...................................................................
10-4
Format of Prescaler Mode Register 5 (PRM5) .................................................................................
10-5
Format of Prescaler Mode Register 6 (PRM6) .................................................................................
10-6
Timing of Interval Timer Operation ....................................................................................................
10-7
Timing of Operation Based on CRn0 Transitions ..............................................................................
10-8
Cascade Connection Mode with 16-Bit Resolution ...........................................................................
10-9
Start Timing of 8-Bit Timer Counter ..................................................................................................
10-10
Timing After the Compare Register Changes During Timer Counting ..............................................
11-1
Block Diagram of Watch Timer .........................................................................................................
11-2
Format of Watch Timer Mode Control Register (WTM) ....................................................................
11-3
Operation Timing of Watch Timer/Interval Timer ...............................................................................
12-1
Block Diagram of Watchdog Timer ...................................................................................................
12-2
Format of Watchdog Timer Mode Register (WDM) ...........................................................................
13-1
Block Diagram of A/D Converter .......................................................................................................
13-2
Format of A/D Converter Mode Register (ADM) ...............................................................................
13-3
Format of A/D Converter Input Selection Register (ADIS) ................................................................
13-4
Basic Operations of A/D Converter ...................................................................................................
13-5
Relationship Between Analog Input Voltage and A/D Conversion Result .........................................
13-6
A/D Conversion Operation by Hardware Start (When Falling Edge Is Specified) ............................
22
LIST OF FIGURES (3/8)
Title
User's Manual U12697EJ3V0UM
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